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Message-ID: <1693557645-2728466-2-git-send-email-srinivas.goud@amd.com>
Date: Fri, 1 Sep 2023 14:10:43 +0530
From: Srinivas Goud <srinivas.goud@....com>
To: <wg@...ndegger.com>, <mkl@...gutronix.de>, <davem@...emloft.net>,
<edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <p.zabel@...gutronix.de>
CC: <git@....com>, <michal.simek@....com>, <linux-can@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<devicetree@...r.kernel.org>, <appana.durga.rao@...inx.com>,
<naga.sureshkumar.relli@...inx.com>,
"Srinivas Goud" <srinivas.goud@....com>
Subject: [PATCH v4 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc'
ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller.
Part of this feature configuration and counter registers added in
IP for 1bit/2bit ECC errors.
xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller
node if ECC block enabled in the HW
Signed-off-by: Srinivas Goud <srinivas.goud@....com>
---
Changes in v4:
Fix binding check warning
Update property description
Changes in v3:
Update commit description
Changes in v2:
None
Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
index 64d57c3..50a2671 100644
--- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
+++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
@@ -49,6 +49,10 @@ properties:
resets:
maxItems: 1
+ xlnx,has-ecc:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: CAN Tx and Rx fifo has ECC (AXI CAN)
+
required:
- compatible
- reg
@@ -137,6 +141,7 @@ examples:
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ xlnx,has-ecc;
};
- |
--
2.1.1
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