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Message-ID: <833a4908-6bc2-4b66-9ace-4beab186e634@roeck-us.net>
Date:   Sat, 2 Sep 2023 07:16:22 -0700
From:   Guenter Roeck <linux@...ck-us.net>
To:     Naresh Solanki <naresh.solanki@...ements.com>
Cc:     Jean Delvare <jdelvare@...e.com>,
        krzysztof.kozlowski+dt@...aro.org, linux-hwmon@...r.kernel.org,
        Patrick Rudolph <patrick.rudolph@...ements.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 3/3] hwmon: (pmbus/tda38640) Add workaround for SVID
 mode

On Thu, Aug 31, 2023 at 09:07:29PM +0200, Naresh Solanki wrote:
> From: Patrick Rudolph <patrick.rudolph@...ements.com>
> 
> TDA38640 can operate in either PMBus mode or SVID mode.
> 
> In SVID mode, by design ENABLE pin is the only option for controlling
> the output rail i.e., ENABLE pin is chained to power good of another
> reglator & FPGA.
> 
> In cases where the chip is configured for SVID mode, and the ENABLE pin
> is set at a fixed level or is left unconnected (with an internal
> pull-down), while requiring software control, the following
> workaround is necessary.
> 
> The workaround utilizes ENABLE pin polarity flipping to control
> output rail.
> 
> If property 'infineon,en-pin-fixed-level' is specified then
> determine if chip is in SVID mode by checking BIT15 of MTP memory offset
> 0x44 as described in the datasheet.
> 
> If chip is in SVID mode then apply the workaround by
> 1. Determine EN pin level
> 2. Maps BIT7 of OPERATION(01h) to EN_PIN_POLARITY(BIT1) of
>    PB_ON_OFF_CONFIG.
> 
> Signed-off-by: Patrick Rudolph <patrick.rudolph@...ements.com>
> Signed-off-by: Naresh Solanki <Naresh.Solanki@...ements.com>
> ----

Applied to hwmon-next.

Thanks,
Guenter

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