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Message-Id: <20230902-msm8226-i2c6-v1-2-9632b8916789@z3ntu.xyz>
Date: Sat, 02 Sep 2023 19:32:25 +0200
From: Luca Weiss <luca@...tu.xyz>
To: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Luca Weiss <luca@...tu.xyz>
Subject: [PATCH 2/2] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and
blsp1_uart2
Add more busses found on msm8226 SoC.
Signed-off-by: Luca Weiss <luca@...tu.xyz>
---
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
index b6ae4b7936e3..3b6114049e61 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
@@ -230,6 +230,15 @@ blsp1_uart1: serial@...1d000 {
status = "disabled";
};
+ blsp1_uart2: serial@...1e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@...1f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
@@ -313,6 +322,19 @@ blsp1_i2c5: i2c@...27000 {
#size-cells = <0>;
};
+ blsp1_i2c6: i2c@...28000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9928000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c6_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
cci: cci@...0c000 {
compatible = "qcom,msm8226-cci";
#address-cells = <1>;
@@ -460,6 +482,13 @@ blsp1_i2c5_pins: blsp1-i2c5-state {
bias-disable;
};
+ blsp1_i2c6_pins: blsp1-i2c6-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci_default: cci-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c0";
--
2.42.0
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