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Message-ID: <ZPUXhe7ogxvaB6Eg@x1>
Date: Sun, 3 Sep 2023 16:32:21 -0700
From: Drew Fustini <dfustini@...libre.com>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
inux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: thead: set dma-noncoherent to soc bus
On Sun, Aug 20, 2023 at 07:53:53PM +0800, Jisheng Zhang wrote:
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 56a73134b49e..58108f0eb3fd 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
> interrupt-parent = <&plic>;
> #address-cells = <2>;
> #size-cells = <2>;
> + dma-noncoherent;
> ranges;
>
> plic: interrupt-controller@...8000000 {
> --
> 2.40.1
>
Tested-by: Drew Fustini <dfustini@...libre.com>
I tried this on the BeagleV Ahead. They system booted as expected and I
did not notice any problems in the boot log.
Are there other patches such as the dwmac series that I should test this
with?
Also, I think this might have missed patchwork since the original email
had a typo for the list, so it might be good to resend it?
Thanks,
Drew
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