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Message-Id: <20230905123309.775854-1-jtp.park@samsung.com>
Date:   Tue,  5 Sep 2023 21:33:09 +0900
From:   Jeongtae Park <jtp.park@...sung.com>
To:     linux-cxl@...r.kernel.org,
        Jonathan Cameron <jonathan.cameron@...wei.com>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Will Deacon <will@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Kyungsan Kim <ks0204.kim@...sung.com>,
        Wonjae Lee <wj28.lee@...sung.com>,
        Hojin Nam <hj96.nam@...sung.com>,
        Junhyeok Im <junhyeok.im@...sung.com>,
        Jehoon Park <jehoon.park@...sung.com>,
        Jeongtae Park <jtp.park@...sung.com>
Subject: [PATCH] perf: CXL: fix mismatched number of counters mask

The number of Count Units field is described as 6 bits long
in the CXL 3.0 specification. However, its mask value was
only declared as 5 bits long.

Signed-off-by: Jeongtae Park <jtp.park@...sung.com>
---
 drivers/perf/cxl_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 0a8f597e695b..365d964b0f6a 100644
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -25,7 +25,7 @@
 #include "../cxl/pmu.h"
 
 #define CXL_PMU_CAP_REG			0x0
-#define   CXL_PMU_CAP_NUM_COUNTERS_MSK			GENMASK_ULL(4, 0)
+#define   CXL_PMU_CAP_NUM_COUNTERS_MSK			GENMASK_ULL(5, 0)
 #define   CXL_PMU_CAP_COUNTER_WIDTH_MSK			GENMASK_ULL(15, 8)
 #define   CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK		GENMASK_ULL(24, 20)
 #define   CXL_PMU_CAP_FILTERS_SUP_MSK			GENMASK_ULL(39, 32)

base-commit: fe77cc2e5a6a7c85f5c6ef8a39d7694ffc7f41c9
-- 
2.34.1

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