linux-kernel - Re: [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property

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Message-ID: <932355b4-7d43-a465-a2da-8dded8e2d069@arm.com>
Date:   Tue, 5 Sep 2023 12:17:51 +0100
From:   Robin Murphy <robin.murphy@....com>
To:     Lorenzo Pieralisi <lpieralisi@...nel.org>,
        linux-kernel@...r.kernel.org
Cc:     Rob Herring <robh@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Fang Xiang <fangxiang3@...omi.com>,
        Marc Zyngier <maz@...nel.org>
Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add
 dma-noncoherent property

On 05/09/2023 11:47 am, Lorenzo Pieralisi wrote:
> The GIC v3 specifications allow redistributors and ITSes interconnect
> ports used to access memory to be wired up in a way that makes the
> respective initiators/memory observers non-coherent.
> 
> Add the standard dma-noncoherent property to the GICv3 bindings to
> allow firmware to describe the redistributors/ITSes components and
> interconnect ports behaviour in system designs where the redistributors
> and ITSes are not coherent with the CPU.
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
> Cc: Rob Herring <robh@...nel.org>
> ---
>   .../bindings/interrupt-controller/arm,gic-v3.yaml         | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> index 39e64c7f6360..0a81ae4519a6 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> @@ -106,6 +106,10 @@ properties:
>       $ref: /schemas/types.yaml#/definitions/uint32
>       maximum: 4096
>   
> +  dma-noncoherent:
> +    description: |
> +      Present if the GIC redistributors are not cache coherent with the CPU.

I wonder if it's worth being a bit more specific here, e.g. "if the GIC 
{redistributors,ITS} permit programming cacheable inner-shareable memory 
attributes, but are connected to a non-coherent downstream 
interconnect." That might help clarify why the negative property, which 
could seem a bit backwards at first glance, and that it's not so 
important in the cases where the GIC itself is fundamentally 
non-coherent anyway (which *is* software-discoverable).

Otherwise, this is the same approach that I like and have previously 
lobbied for, so obviously I approve :)

(plus I do think it's the right shape to be able to slot an equivalent 
field into ACPI MADT entries without *too* much bother)

Thanks,
Robin.

> +
>     msi-controller:
>       description:
>         Only present if the Message Based Interrupt functionality is
> @@ -193,6 +197,10 @@ patternProperties:
>         compatible:
>           const: arm,gic-v3-its
>   
> +      dma-noncoherent:
> +        description: |
> +          Present if the GIC ITS is not cache coherent with the CPU.
> +
>         msi-controller: true
>   
>         "#msi-cells":