lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZPeGuCJ9xWF+EGHY@gmail.com>
Date:   Tue, 5 Sep 2023 21:51:20 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     kan.liang@...ux.intel.com
Cc:     peterz@...radead.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org,
        Stephane Eranian <eranian@...gle.com>,
        Yunying Sun <yunying.sun@...el.com>
Subject: Re: [PATCH V2] perf/x86/uncore: Correct the number of CHAs on EMR


* kan.liang@...ux.intel.com <kan.liang@...ux.intel.com> wrote:

> From: Kan Liang <kan.liang@...ux.intel.com>
> 
> Starting from SPR, the basic uncore PMON information is retrieved from
> the discovery table (resides in an MMIO space populated by BIOS). It is
> called the discovery method. The existing value of the type->num_boxes
> is from the discovery table.
> 
> On some SPR variants, there is a firmware bug. So the value from the
> discovery table is incorrect. We use the value from the
> SPR_MSR_UNC_CBO_CONFIG to replace the one from the discovery table.
> Commit 38776cc45eb7 ("perf/x86/uncore: Correct the number of CHAs on SPR")
> 
> Unfortunately, the SPR_MSR_UNC_CBO_CONFIG isn't available for the EMR
> XCC (Always returns 0). But the above firmware bug
> doesn't impact the EMR XCC. Don't let the value from the MSR replace
> the existing value from the discovery table.
> 
> Fixes: 38776cc45eb7 ("perf/x86/uncore: Correct the number of CHAs on SPR")
> Reported-by: Stephane Eranian <eranian@...gle.com>
> Reported-by: Yunying Sun <yunying.sun@...el.com>
> Tested-by: Yunying Sun <yunying.sun@...el.com>
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index 4d349986f76a..8250f0f59c2b 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -6474,8 +6474,18 @@ void spr_uncore_cpu_init(void)
>  
>  	type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
>  	if (type) {
> +		/*
> +		 * The value from the discovery table (stored in the type->num_boxes
> +		 * of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a
> +		 * firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.
> +		 */
>  		rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
> -		type->num_boxes = num_cbo;
> +		/*
> +		 * The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact
> +		 * the EMR XCC. Don't let the value from the MSR replace the existing value.
> +		 */
> +		if (num_cbo)
> +			type->num_boxes = num_cbo;

Thank you, that's a perfect description of the quirk - applied to 
tip:perf/urgent.

	Ingo

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ