linux-kernel - Re: [PATCH RESEND 0/7] Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller

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Message-ID: <131ad20f-ed64-11b8-e1d8-f48990115b21@quicinc.com>
Date:   Wed, 6 Sep 2023 10:30:51 +0530
From:   Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
To:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Jassi Brar <jassisinghbrar@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen Boyd" <sboyd@...nel.org>,
        Sricharan Ramabadhran <quic_srichara@...cinc.com>,
        Anusha Rao <quic_anusha@...cinc.com>,
        Devi Priya <quic_devipriy@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH RESEND 0/7] Add GPLL0 as clock provider for the Qualcomm's
 IPQ mailbox controller


On 9/6/2023 10:26 AM, Kathiravan Thirumoorthy wrote:
> Currently mailbox controller takes the XO and APSS PLL as the input. It
> can take the GPLL0 also as an input. This patch series adds the same and
> fixes the issue caused by this.
>
> Once the cpufreq driver is up, it tries to bump up the cpu frequency
> above 800MHz, while doing so system is going to unusable state. Reason
> being, with the GPLL0 included as clock source, clock framework tries to
> achieve the required rate with the possible parent and since GPLL0 carries
> the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting
> changed, causing the issue.
>
> First half of the series, removes the CLK_SET_RATE_PARENT flag from the
> PLL clocks since the PLL clock rates shouldn't be changed. Another
> half, add the necessary support to include the GPLL0 as clock provider
> for mailbox and accomodate the changes in APSS clock driver.
>
> This is also the preparatory series to enable the CPUFreq on IPQ5332
> SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to
> switch between the frequencies we need to park the APSS PLL in safe
> source, here it is GPLL0 and then shutdown and bring up the APSS PLL in
> the desired rate.
>
> For IPQ5332 SoC, this series depends on the below patch
> https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/


My bad.. This is not a 'resend', this is V1.. I'm trying to get used to 
b4 and messed up... Will rectify it in future.


>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
> ---
> Kathiravan Thirumoorthy (7):
>        clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox
>        clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
>        arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox
>
>   .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml         | 2 ++
>   arch/arm64/boot/dts/qcom/ipq5332.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq9574.dtsi                              | 4 ++--
>   drivers/clk/qcom/apss-ipq6018.c                                    | 3 +++
>   drivers/clk/qcom/gcc-ipq5332.c                                     | 2 --
>   drivers/clk/qcom/gcc-ipq6018.c                                     | 7 -------
>   drivers/clk/qcom/gcc-ipq8074.c                                     | 7 -------
>   drivers/clk/qcom/gcc-ipq9574.c                                     | 4 ----
>   10 files changed, 13 insertions(+), 28 deletions(-)
> ---
> base-commit: a47fc304d2b678db1a5d760a7d644dac9b067752
> change-id: 20230904-gpll_cleanup-8b3e8b058c8b
>
> Best regards,