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Message-ID: <SN7PR12MB7201AC85590CB85F6EE00CCA8BEFA@SN7PR12MB7201.namprd12.prod.outlook.com>
Date: Wed, 6 Sep 2023 08:16:46 +0000
From: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>
To: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
CC: "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
"robh@...nel.org" <robh@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>,
"Simek, Michal" <michal.simek@....com>,
"Gogada, Bharat Kumar" <bharat.kumar.gogada@....com>
Subject: RE: [PATCH v7 1/3] PCI: xilinx-cpm: Move interrupt bit definitions to
common header
Hi Bjorn,
Please provide update on this patch.
Regards,
Thippeswamy H
> -----Original Message-----
> From: Thippeswamy Havalige <thippeswamy.havalige@....com>
> Sent: Wednesday, August 30, 2023 2:37 PM
> To: linux-kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> bhelgaas@...gle.com; krzysztof.kozlowski+dt@...aro.org;
> devicetree@...r.kernel.org; linux-pci@...r.kernel.org
> Cc: lpieralisi@...nel.org; robh@...nel.org; conor+dt@...nel.org; Simek,
> Michal <michal.simek@....com>; Gogada, Bharat Kumar
> <bharat.kumar.gogada@....com>; Havalige, Thippeswamy
> <thippeswamy.havalige@....com>
> Subject: [PATCH v7 1/3] PCI: xilinx-cpm: Move interrupt bit definitions to
> common header
>
> Rename Xilinx interrupt bit definitions so they are not CPM-specific. Move the
> definitions to pcie-xilinx-common.h where they can be shared between pcie-
> xilinx-cpm and the new xilinx-xdma driver.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@....com>
> ---
> changes in v7:
> - None
> changes in v6:
> - subject line and commit message
> changes in v5:
> - None
> changes in v4:
> - None
> changes in v3:
> - changed licensing year to 2023
> ---
> drivers/pci/controller/pcie-xilinx-common.h | 30 +++++++++++++++++++++++
> drivers/pci/controller/pcie-xilinx-cpm.c | 38 ++++++-----------------------
> 2 files changed, 37 insertions(+), 31 deletions(-) create mode 100644
> drivers/pci/controller/pcie-xilinx-common.h
>
> diff --git a/drivers/pci/controller/pcie-xilinx-common.h
> b/drivers/pci/controller/pcie-xilinx-common.h
> new file mode 100644
> index 0000000..e97d272
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-xilinx-common.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * (C) Copyright 2023, Xilinx, Inc.
> + */
> +
> +#include <linux/pci.h>
> +#include <linux/pci-ecam.h>
> +#include <linux/platform_device.h>
> +
> +/* Interrupt registers definitions */
> +#define XILINX_PCIE_INTR_LINK_DOWN 0
> +#define XILINX_PCIE_INTR_HOT_RESET 3
> +#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT 4
> +#define XILINX_PCIE_INTR_CFG_TIMEOUT 8
> +#define XILINX_PCIE_INTR_CORRECTABLE 9
> +#define XILINX_PCIE_INTR_NONFATAL 10
> +#define XILINX_PCIE_INTR_FATAL 11
> +#define XILINX_PCIE_INTR_CFG_ERR_POISON 12
> +#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15
> +#define XILINX_PCIE_INTR_INTX 16
> +#define XILINX_PCIE_INTR_PM_PME_RCVD 17
> +#define XILINX_PCIE_INTR_SLV_UNSUPP 20
> +#define XILINX_PCIE_INTR_SLV_UNEXP 21
> +#define XILINX_PCIE_INTR_SLV_COMPL 22
> +#define XILINX_PCIE_INTR_SLV_ERRP 23
> +#define XILINX_PCIE_INTR_SLV_CMPABT 24
> +#define XILINX_PCIE_INTR_SLV_ILLBUR 25
> +#define XILINX_PCIE_INTR_MST_DECERR 26
> +#define XILINX_PCIE_INTR_MST_SLVERR 27
> +#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT 28
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> b/drivers/pci/controller/pcie-xilinx-cpm.c
> index 4a787a9..a0f5e1d 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -16,11 +16,9 @@
> #include <linux/of_address.h>
> #include <linux/of_pci.h>
> #include <linux/of_platform.h>
> -#include <linux/pci.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci-ecam.h>
>
> #include "../pci.h"
> +#include "pcie-xilinx-common.h"
>
> /* Register definitions */
> #define XILINX_CPM_PCIE_REG_IDR 0x00000E10
> @@ -38,29 +36,7 @@
> #define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
> #define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
>
> -/* Interrupt registers definitions */
> -#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
> -#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
> -#define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4
> -#define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
> -#define XILINX_CPM_PCIE_INTR_CORRECTABLE 9
> -#define XILINX_CPM_PCIE_INTR_NONFATAL 10
> -#define XILINX_CPM_PCIE_INTR_FATAL 11
> -#define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12
> -#define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15
> -#define XILINX_CPM_PCIE_INTR_INTX 16
> -#define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17
> -#define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20
> -#define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21
> -#define XILINX_CPM_PCIE_INTR_SLV_COMPL 22
> -#define XILINX_CPM_PCIE_INTR_SLV_ERRP 23
> -#define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24
> -#define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25
> -#define XILINX_CPM_PCIE_INTR_MST_DECERR 26
> -#define XILINX_CPM_PCIE_INTR_MST_SLVERR 27
> -#define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28
> -
> -#define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x)
> +#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)
>
> #define XILINX_CPM_PCIE_IMR_ALL_MASK \
> ( \
> @@ -323,7 +299,7 @@ static void xilinx_cpm_pcie_event_flow(struct
> irq_desc *desc) }
>
> #define _IC(x, s) \
> - [XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s }
> + [XILINX_PCIE_INTR_ ## x] = { __stringify(x), s }
>
> static const struct {
> const char *sym;
> @@ -359,9 +335,9 @@ static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq,
> void *dev_id)
> d = irq_domain_get_irq_data(port->cpm_domain, irq);
>
> switch (d->hwirq) {
> - case XILINX_CPM_PCIE_INTR_CORRECTABLE:
> - case XILINX_CPM_PCIE_INTR_NONFATAL:
> - case XILINX_CPM_PCIE_INTR_FATAL:
> + case XILINX_PCIE_INTR_CORRECTABLE:
> + case XILINX_PCIE_INTR_NONFATAL:
> + case XILINX_PCIE_INTR_FATAL:
> cpm_pcie_clear_err_interrupts(port);
> fallthrough;
>
> @@ -466,7 +442,7 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie
> *port)
> }
>
> port->intx_irq = irq_create_mapping(port->cpm_domain,
> - XILINX_CPM_PCIE_INTR_INTX);
> + XILINX_PCIE_INTR_INTX);
> if (!port->intx_irq) {
> dev_err(dev, "Failed to map INTx interrupt\n");
> return -ENXIO;
> --
> 1.8.3.1
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