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Message-ID: <CAHVXubiENHt36LrcSBoNU0rAMQ8EoT6tde9M8vLP3Hw2nwMm8g@mail.gmail.com>
Date: Wed, 6 Sep 2023 14:01:38 +0200
From: Alexandre Ghiti <alexghiti@...osinc.com>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>,
Will Deacon <will@...nel.org>,
"Aneesh Kumar K . V" <aneesh.kumar@...ux.ibm.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Nick Piggin <npiggin@...il.com>,
Peter Zijlstra <peterz@...radead.org>,
Mayuresh Chitale <mchitale@...tanamicro.com>,
Vincent Chen <vincent.chen@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, linux-arch@...r.kernel.org,
linux-mm@...ck.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Andrew Jones <ajones@...tanamicro.com>
Subject: Re: [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range()
Hi Prabhakar,
On Wed, Sep 6, 2023 at 1:49 PM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
>
> Hi Alexandre,
>
> On Tue, Aug 1, 2023 at 9:58 AM Alexandre Ghiti <alexghiti@...osinc.com> wrote:
> >
> > This function used to simply flush the whole tlb of all harts, be more
> > subtile and try to only flush the range.
> >
> > The problem is that we can only use PAGE_SIZE as stride since we don't know
> > the size of the underlying mapping and then this function will be improved
> > only if the size of the region to flush is < threshold * PAGE_SIZE.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@...osinc.com>
> > Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> > ---
> > arch/riscv/include/asm/tlbflush.h | 11 +++++-----
> > arch/riscv/mm/tlbflush.c | 34 +++++++++++++++++++++++--------
> > 2 files changed, 31 insertions(+), 14 deletions(-)
> >
> After applying this patch, I am seeing module load issues on RZ/Five
> (complete log [0]). I am testing defconfig + [1] (rz/five related
> configs).
>
> Any pointers on what could be an issue here?
Can you give me the exact version of the kernel you use? The trap
addresses are vmalloc addresses, and a fix for those landed very late
in the release cycle.
>
> [0] https://paste.debian.net/1291116/
> [1] https://paste.debian.net/1291118/
>
> Cheers,
> Prabhakar
>
> > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
> > index f5c4fb0ae642..7426fdcd8ec5 100644
> > --- a/arch/riscv/include/asm/tlbflush.h
> > +++ b/arch/riscv/include/asm/tlbflush.h
> > @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
> > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
> > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> > unsigned long end);
> > +void flush_tlb_kernel_range(unsigned long start, unsigned long end);
> > #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> > #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> > @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
> > local_flush_tlb_all();
> > }
> >
> > -#define flush_tlb_mm(mm) flush_tlb_all()
> > -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> > -#endif /* !CONFIG_SMP || !CONFIG_MMU */
> > -
> > /* Flush a range of kernel pages */
> > static inline void flush_tlb_kernel_range(unsigned long start,
> > unsigned long end)
> > {
> > - flush_tlb_all();
> > + local_flush_tlb_all();
> > }
> >
> > +#define flush_tlb_mm(mm) flush_tlb_all()
> > +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> > +#endif /* !CONFIG_SMP || !CONFIG_MMU */
> > +
> > #endif /* _ASM_RISCV_TLBFLUSH_H */
> > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> > index 0c955c474f3a..687808013758 100644
> > --- a/arch/riscv/mm/tlbflush.c
> > +++ b/arch/riscv/mm/tlbflush.c
> > @@ -120,18 +120,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> > unsigned long size, unsigned long stride)
> > {
> > struct flush_tlb_range_data ftd;
> > - struct cpumask *cmask = mm_cpumask(mm);
> > - unsigned int cpuid;
> > + struct cpumask *cmask, full_cmask;
> > bool broadcast;
> >
> > - if (cpumask_empty(cmask))
> > - return;
> > + if (mm) {
> > + unsigned int cpuid;
> > +
> > + cmask = mm_cpumask(mm);
> > + if (cpumask_empty(cmask))
> > + return;
> > +
> > + cpuid = get_cpu();
> > + /* check if the tlbflush needs to be sent to other CPUs */
> > + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> > + } else {
> > + cpumask_setall(&full_cmask);
> > + cmask = &full_cmask;
> > + broadcast = true;
> > + }
> >
> > - cpuid = get_cpu();
> > - /* check if the tlbflush needs to be sent to other CPUs */
> > - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> > if (static_branch_unlikely(&use_asid_allocator)) {
> > - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask;
> > + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0;
> >
> > if (broadcast) {
> > if (riscv_use_ipi_for_rfence()) {
> > @@ -165,7 +174,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> > }
> > }
> >
> > - put_cpu();
> > + if (mm)
> > + put_cpu();
> > }
> >
> > void flush_tlb_mm(struct mm_struct *mm)
> > @@ -196,6 +206,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> >
> > __flush_tlb_range(vma->vm_mm, start, end - start, stride_size);
> > }
> > +
> > +void flush_tlb_kernel_range(unsigned long start, unsigned long end)
> > +{
> > + __flush_tlb_range(NULL, start, end, PAGE_SIZE);
> > +}
> > +
> > #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> > unsigned long end)
> > --
> > 2.39.2
> >
> >
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