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Message-ID: <e7bd3aa9-b8ee-4b8a-2354-e786f9a9ff47@quicinc.com>
Date:   Thu, 7 Sep 2023 09:06:17 +0530
From:   Krishna Kurapati PSSNV <quic_kriskura@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Andy Gross <agross@...nel.org>,
        "Bjorn Andersson" <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Felipe Balbi <balbi@...nel.org>,
        Wesley Cheng <quic_wcheng@...cinc.com>,
        Johan Hovold <johan@...nel.org>,
        Mathias Nyman <mathias.nyman@...el.com>
CC:     <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <quic_pkondeti@...cinc.com>, <quic_ppratap@...cinc.com>,
        <quic_jackp@...cinc.com>, <ahalaney@...hat.com>,
        <quic_shazhuss@...cinc.com>
Subject: Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first
 port of tertiary usb controller



On 9/6/2023 10:28 PM, Konrad Dybcio wrote:
> On 28.08.2023 15:30, Krishna Kurapati wrote:
>> From: Andrew Halaney <ahalaney@...hat.com>
>>
>> There is now support for the multiport USB controller this uses so
>> enable it.
>>
>> The board only has a single port hooked up (despite it being wired up to
>> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
>> which by default on boot is selected to mux properly. Grab the gpio
>> controlling that and ensure it stays in the right position so USB 2.0
>> continues to be routed from the external port to the SoC.
>>
>> Co-developed-by: Andrew Halaney <ahalaney@...hat.com>
>> Signed-off-by: Andrew Halaney <ahalaney@...hat.com>
>> [Krishna: Rebased on top of usb-next]
>> Co-developed-by: Krishna Kurapati <quic_kriskura@...cinc.com>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
>> ---
> Is there any benefit to removing the other ports?
> 
> i.e. are ports 1-3 not parked properly by the dwc3 driver if
> they're never connected to anything?
> 
Hi Konrad,

  Whether or not the phy is connected to a port, the controller would 
modify the GUSB2PHYCFG/GUSB3PIPECTL registers. But if we don't specify 
only one phy and let phys from base DTSI take effect (4 HS / 2 SS), we 
would end up initializing and powering on phy's which are never 
connected to a port. To avoid that we need to specify only one phy for 
this platform.

Regards,
Krishna,

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