linux-kernel - Re: [PATCH v2, 3/3] drm/mediatek: dsi: Add dsi cmdq

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Message-ID: <411ddbf95e2c2298b84899065691d478069ec273.camel@mediatek.com>
Date:   Thu, 7 Sep 2023 06:21:49 +0000
From:   CK Hu (胡俊光) <ck.hu@...iatek.com>
To:     Shuijing Li (李水静) 
        <Shuijing.Li@...iatek.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
        "daniel@...ll.ch" <daniel@...ll.ch>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "airlied@...il.com" <airlied@...il.com>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "angelogioacchino.delregno@...labora.com" 
        <angelogioacchino.delregno@...labora.com>
CC:     "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Jitao Shi (石记涛) <jitao.shi@...iatek.com>
Subject: Re: [PATCH v2, 3/3] drm/mediatek: dsi: Add dsi cmdq_ctl to send panel
 initial code

Hi, Shuijing:

On Fri, 2023-06-16 at 15:36 +0800, Shuijing Li wrote:
> For mt8188, add dsi cmdq reg control to send long packets to panel
> initialization.

If possible, describe more about WHY mt8188 need this but other SoC
does not need this.

> 
> Signed-off-by: Shuijing Li <shuijing.li@...iatek.com>
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> ---
> Changes in v2:
> use mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
> directly,
> per suggestion from the previous thread:
> 
https://lore.kernel.org/lkml/015f4c60-ed77-9e1f-8a6b-cda6e4f6ac93@gmail.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 500a3054282d..8b43d9f48178 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -86,6 +86,7 @@
>  
>  #define DSI_CMDQ_SIZE		0x60
>  #define CMDQ_SIZE			0x3f
> +#define CMDQ_SIZE_SEL			BIT(15)
>  
>  #define DSI_HSTX_CKL_WC		0x64
>  
> @@ -178,6 +179,7 @@ struct mtk_dsi_driver_data {
>  	const u32 reg_cmdq_off;
>  	bool has_shadow_ctl;
>  	bool has_size_ctl;
> +	bool cmdq_long_packet_ctl;
>  };
>  
>  struct mtk_dsi {
> @@ -996,6 +998,8 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi,
> const struct mipi_dsi_msg *msg)
>  
>  	mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
>  	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> +	if (dsi->driver_data->cmdq_long_packet_ctl)
> +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL,
> CMDQ_SIZE_SEL);
>  }
>  
>  static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
> @@ -1200,18 +1204,21 @@ static const struct mtk_dsi_driver_data
> mt8183_dsi_driver_data = {
>  	.reg_cmdq_off = 0x200,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = false,

Global variable default value is 0, so this modification could be
dropped.

>  };
>  
>  static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
>  	.reg_cmdq_off = 0xd00,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = false,

Ditto.

Regards,
CK

>  };
>  
>  static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
>  	.reg_cmdq_off = 0xd00,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = true,
>  };
>  
>  static const struct of_device_id mtk_dsi_of_match[] = {