linux-kernel - Re: [PATCH bpf-next v2 2/8] arm32, bpf: add support for sign-extension load instruction

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Message-ID: <ZPmNVrXwJ1Q75CV+@shell.armlinux.org.uk>
Date:   Thu, 7 Sep 2023 09:44:06 +0100
From:   "Russell King (Oracle)" <linux@...linux.org.uk>
To:     Puranjay Mohan <puranjay12@...il.com>
Cc:     Alexei Starovoitov <ast@...nel.org>,
        Daniel Borkmann <daniel@...earbox.net>,
        Andrii Nakryiko <andrii@...nel.org>,
        Martin KaFai Lau <martin.lau@...ux.dev>,
        Song Liu <song@...nel.org>,
        Yonghong Song <yonghong.song@...ux.dev>,
        John Fastabend <john.fastabend@...il.com>,
        KP Singh <kpsingh@...nel.org>,
        Stanislav Fomichev <sdf@...gle.com>,
        Hao Luo <haoluo@...gle.com>, Jiri Olsa <jolsa@...nel.org>,
        Shubham Bansal <illusionist.neo@...il.com>,
        Mykola Lysenko <mykolal@...com>, Shuah Khan <shuah@...nel.org>,
        bpf@...r.kernel.org, linux-kselftest@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH bpf-next v2 2/8] arm32, bpf: add support for
 sign-extension load instruction

On Wed, Sep 06, 2023 at 06:33:14PM +0000, Puranjay Mohan wrote:
> The cpuv4 added the support of an instruction that is similar to load
> but also sign-extends the result after the load.
> 
> BPF_MEMSX | <size> | BPF_LDX means dst = *(signed size *) (src + offset)
> here <size> can be one of BPF_B, BPF_H, BPF_W.
> 
> ARM32 has instructions to load a byte or a half word with sign
> extension into a 32bit register. As the JIT uses two 32 bit registers
> to simulate a 64-bit BPF register, an extra instruction is emitted to
> sign-extent the result up to the second register.
> 
> Signed-off-by: Puranjay Mohan <puranjay12@...il.com>

Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>

but see below...

Thanks!

> +static inline void emit_ldsx_r(const s8 dst[], const s8 src,
> +			       s16 off, struct jit_ctx *ctx, const u8 sz){
> +	const s8 *tmp = bpf2a32[TMP_REG_1];
> +	const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
> +	s8 rm = src;
> +	int add_off;
> +
> +	if (!is_ldst_imm8(off, sz)) {

I think a comment here would be useful:
		/* offset does not fit in the load/store immediate,
		 * construct an ADD instruction to apply the offset.
		 */

otherwise I'm sure someone will question why we aren't handling the zero
case below... since zero will fit in the load/store immediate.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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