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Message-ID: <e0b6ddeb-7129-d76f-0584-112d79e3a1fb@ti.com>
Date: Thu, 7 Sep 2023 20:00:16 +0530
From: "J, KEERTHY" <j-keerthy@...com>
To: "Kumar, Udit" <u-kumar1@...com>, <robh+dt@...nel.org>, <nm@...com>,
<vigneshr@...com>, <conor+dt@...nel.org>, <kristo@...nel.org>,
<rzysztof.kozlowski+dt@...aro.org>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 4/7] arm64: dts: ti: k3-j784s4-main: Add the main
domain watchdog instances
On 9/7/2023 7:44 PM, Kumar, Udit wrote:
> Thanks Keerthy,
>
> On 9/7/2023 5:22 PM, Keerthy wrote:
>> There are totally 19 instances of watchdog module. One each for the
>> 8 A72 cores, one each for the 4 C7x cores, 1 for the GPU, 1 each
>> for the 6 R5F cores in the main domain. Keeping only the A72 instances
>> enabled and disabling the rest by default.
>>
>> Signed-off-by: Keerthy <j-keerthy@...com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 182 +++++++++++++++++++++
>> 1 file changed, 182 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 7f7eab348520..66ab947a1081 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -1574,4 +1574,186 @@
>> reg = <0x00 0x700000 0x00 0x1000>;
>> ti,esm-pins = <688>, <689>;
>> };
>> +
>> + watchdog0: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2200000 0x00 0x100>;
>> + clocks = <&k3_clks 348 1>;
>> + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 348 0>;
>> + assigned-clock-parents = <&k3_clks 348 4>;
>> + };
>
> In ESM, patch I see only output of 2 watchdog in cascaded for reset.
>
> if you want to keep enable other wdt, then IMO they should be able to
> reset the core/SOC
>
> on timeout
I can add the other ESM events to the ESM node to enable that. I will
wait if there are more comments. If this is the only one comment i will
post a v3 of the esm patch.
- Keerthy
>
>
>> +
>> + [..]};
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