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Message-ID: <82a82449-3af0-4756-881a-b31b6b187e6c@sifive.com>
Date: Wed, 6 Sep 2023 21:48:35 -0500
From: Samuel Holland <samuel.holland@...ive.com>
To: Yu Chien Peter Lin <peterlin@...estech.com>
Cc: ajones@...tanamicro.com, heiko@...ech.de, samuel@...lland.org,
geert+renesas@...der.be, n.shubin@...ro.com, dminus@...estech.com,
ycliang@...estech.com, tim609@...estech.com, locus84@...estech.com,
dylan@...estech.com, linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu,
conor.dooley@...rochip.com, atishp@...shpatra.org,
anup@...infault.org, prabhakar.mahadev-lad.rj@...renesas.com
Subject: Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata
On 2023-09-06 9:16 PM, Yu Chien Peter Lin wrote:
> Before the ratification of Sscofpmf, the Andes PMU extension
> implements the same mechanism and is compatible with existing
> SBI PMU driver of perf to support event sampling and mode
> filtering with programmable hardware performance counters.
>
> This patch adds PMU support for Andes 45-series CPUs by
> introducing a CPU errata.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> Signed-off-by: Locus Wei-Han Chen <locus84@...estech.com>
> Reviewed-by: Charles Ci-Jyun Wu <dminus@...estech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@...estech.com>
> ---
> arch/riscv/Kconfig.errata | 13 ++++++++
> arch/riscv/errata/andes/errata.c | 45 +++++++++++++++++++++++++++-
> arch/riscv/include/asm/errata_list.h | 43 ++++++++++++++++++++++++--
> drivers/perf/riscv_pmu_sbi.c | 20 +++++++++----
> 4 files changed, 111 insertions(+), 10 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 92c779764b27..a342b209c169 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -21,6 +21,19 @@ config ERRATA_ANDES_CMO
>
> If you don't know what to do here, say "Y".
>
> +config ERRATA_ANDES_PMU
> + bool "Apply Andes PMU errata"
> + depends on ERRATA_ANDES && RISCV_PMU_SBI
> + default y
> + help
> + The Andes 45-series cores implement a PMU overflow extension
> + very similar to the core SSCOFPMF extension.
> +
> + This will apply the overflow errata to handle the non-standard
> + behaviour via the regular SBI PMU driver and interface.
> +
> + If you don't know what to do here, say "Y".
> +
> config ERRATA_SIFIVE
> bool "SiFive errata"
> depends on RISCV_ALTERNATIVE
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index d2e1abcac967..19256691f1ba 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -56,11 +56,54 @@ static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
> return true;
> }
>
> +static bool errata_probe_pmu(unsigned int stage,
> + unsigned long arch_id, unsigned long impid)
> +{
> + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_PMU))
> + return false;
> +
> + if ((arch_id & 0xff) != 0x45)
> + return false;
> +
> + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> + return false;
> +
> + return true;
> +}
> +
> +static u32 andes_errata_probe(unsigned int stage,
> + unsigned long archid, unsigned long impid)
> +{
> + u32 cpu_req_errata = 0;
> +
> + if (errata_probe_pmu(stage, archid, impid))
> + cpu_req_errata |= BIT(ERRATA_ANDES_PMU);
> +
> + return cpu_req_errata;
> +}
> +
> void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> unsigned long archid, unsigned long impid,
> unsigned int stage)
> {
> + struct alt_entry *alt;
> + u32 cpu_req_errata = andes_errata_probe(stage, archid, impid);
> + u32 tmp;
> +
> errata_probe_iocp(stage, archid, impid);
>
> - /* we have nothing to patch here ATM so just return back */
> + for (alt = begin; alt < end; alt++) {
> + if (alt->vendor_id != ANDES_VENDOR_ID)
> + continue;
> + if (alt->patch_id >= ERRATA_ANDES_NUMBER)
> + continue;
> +
> + tmp = (1U << alt->patch_id);
> + if (cpu_req_errata & tmp) {
> + mutex_lock(&text_mutex);
> + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
> + alt->alt_len);
> + mutex_unlock(&text_mutex);
> + }
> + }
> }
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 56ab40e64092..bb4c276e2c7f 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -13,7 +13,8 @@
>
> #ifdef CONFIG_ERRATA_ANDES
> #define ERRATA_ANDES_NO_IOCP 0
> -#define ERRATA_ANDES_NUMBER 1
> +#define ERRATA_ANDES_PMU 1
> +#define ERRATA_ANDES_NUMBER 2
> #endif
>
> #ifdef CONFIG_ERRATA_SIFIVE
> @@ -150,15 +151,51 @@ asm volatile(ALTERNATIVE_2( \
> #define THEAD_C9XX_RV_IRQ_PMU 17
> #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
>
> +#define ANDES_RV_IRQ_PMU 18
> +#define ANDES_SLI_CAUSE_BASE 256
> +#define ANDES_CSR_SCOUNTEROF 0x9d4
> +#define ANDES_CSR_SLIE 0x9c4
> +#define ANDES_CSR_SLIP 0x9c5
> +
> #define ALT_SBI_PMU_OVERFLOW(__ovl) \
> -asm volatile(ALTERNATIVE( \
> +asm volatile(ALTERNATIVE_2( \
> "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> - CONFIG_ERRATA_THEAD_PMU) \
> + CONFIG_ERRATA_THEAD_PMU, \
> + "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \
> + ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
> + CONFIG_ERRATA_ANDES_PMU) \
> : "=r" (__ovl) : \
> : "memory")
>
> +#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_num) \
> +asm volatile(ALTERNATIVE( \
> + "csrc " __stringify(CSR_IP) ", %0\n\t", \
> + "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
> + ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
> + CONFIG_ERRATA_ANDES_PMU) \
> + : : "r"(BIT(__irq_num)) \
> + : "memory")
> +
> +#define ALT_SBI_PMU_OVF_DISABLE(__irq_num) \
> +asm volatile(ALTERNATIVE( \
> + "csrc " __stringify(CSR_IE) ", %0\n\t", \
> + "csrc " __stringify(ANDES_CSR_SLIE) ", %0\n\t", \
> + ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
> + CONFIG_ERRATA_ANDES_PMU) \
> + : : "r"(BIT(__irq_num)) \
> + : "memory")
> +
> +#define ALT_SBI_PMU_OVF_ENABLE(__irq_num) \
> +asm volatile(ALTERNATIVE( \
> + "csrs " __stringify(CSR_IE) ", %0\n\t", \
> + "csrs " __stringify(ANDES_CSR_SLIE) ", %0\n\t", \
> + ANDES_VENDOR_ID, ERRATA_ANDES_PMU, \
> + CONFIG_ERRATA_ANDES_PMU) \
> + : : "r"(BIT(__irq_num)) \
> + : "memory")
> +
> #endif /* __ASSEMBLY__ */
>
> #endif
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 9a51053b1f99..8b67f202d2ae 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -687,7 +687,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
> fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
> event = cpu_hw_evt->events[fidx];
> if (!event) {
> - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
> + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_num);
> return IRQ_NONE;
> }
>
> @@ -701,7 +701,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
> * Overflow interrupt pending bit should only be cleared after stopping
> * all the counters to avoid any race condition.
> */
> - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
> + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_num);
>
> /* No overflow bit is set */
> if (!overflow)
> @@ -773,8 +773,8 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
>
> if (riscv_pmu_use_irq) {
> cpu_hw_evt->irq = riscv_pmu_irq;
> - csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
> - csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
> + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_num);
> + ALT_SBI_PMU_OVF_ENABLE(riscv_pmu_irq_num);
> enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
> }
>
> @@ -785,7 +785,7 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
> {
> if (riscv_pmu_use_irq) {
> disable_percpu_irq(riscv_pmu_irq);
> - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
> + ALT_SBI_PMU_OVF_DISABLE(riscv_pmu_irq_num);
> }
>
> /* Disable all counters access for user mode now */
> @@ -809,6 +809,10 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> riscv_cached_mimpid(0) == 0) {
> riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> riscv_pmu_use_irq = true;
> + } else if (IS_ENABLED(CONFIG_ERRATA_ANDES_PMU) &&
> + riscv_cached_mvendorid(0) == ANDES_VENDOR_ID) {
> + riscv_pmu_irq_num = ANDES_RV_IRQ_PMU;
> + riscv_pmu_use_irq = true;
> }
>
> if (!riscv_pmu_use_irq)
> @@ -821,7 +825,11 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> return -ENODEV;
> }
>
> - riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
> + if (IS_ENABLED(CONFIG_ERRATA_ANDES_PMU))
> + riscv_pmu_irq = irq_create_mapping(
> + domain, ANDES_SLI_CAUSE_BASE + riscv_pmu_irq_num);
> + else
> + riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
If the code here needs to be different, then it must check that it is actually
running on an Andes core, not just that the errata Kconfig option is enabled.
However, I suggest setting riscv_pmu_irq_num to the real IRQ number:
riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU;
and then adding a new variable for the mask:
riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
which handles the large IRQ number somewhat more generically, and reduces the
number of bit operations needed elsewhere in the driver.
Or we could use IRQ chip operations here instead of direct CSR acccess. But
maybe the direct CSR access is needed for performance?
Regards,
Samuel
> if (!riscv_pmu_irq) {
> pr_err("Failed to map PMU interrupt for node\n");
> return -ENODEV;
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