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Message-ID: <20230908065847.28382-6-quic_tengfan@quicinc.com>
Date: Fri, 8 Sep 2023 14:58:46 +0800
From: Tengfei Fan <quic_tengfan@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<tglx@...utronix.de>, <maz@...nel.org>, <lee@...nel.org>
CC: <robimarko@...il.com>, <quic_gurus@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_tsoni@...cinc.com>,
<quic_shashim@...cinc.com>, <quic_kaushalk@...cinc.com>,
<quic_tdas@...cinc.com>, <quic_tingweiz@...cinc.com>,
<quic_aiquny@...cinc.com>, <kernel@...cinc.com>,
<quic_bjorande@...cinc.com>, Ajit Pandey <quic_ajipan@...cinc.com>,
Tengfei Fan <quic_tengfan@...cinc.com>
Subject: [PATCH 5/6] arm64: dts: qcom: sm4450: Add RPMH and Global clock controller
From: Ajit Pandey <quic_ajipan@...cinc.com>
Add device node for RPMH and Global clock controller on Qualcomm
SM4450 platform.
Signed-off-by: Ajit Pandey <quic_ajipan@...cinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index eb544d875806..2395b1d655a2 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -367,6 +369,22 @@
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm4450-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+ };
+
+ gcc: clock-controller@...000 {
+ compatible = "qcom,sm4450-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
tcsr_mutex: hwlock@...0000 {
--
2.17.1
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