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Date: Fri, 8 Sep 2023 10:13:35 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Tengfei Fan <quic_tengfan@...cinc.com>, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
tglx@...utronix.de, maz@...nel.org, lee@...nel.org
Cc: robimarko@...il.com, quic_gurus@...cinc.com,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_tsoni@...cinc.com,
quic_shashim@...cinc.com, quic_kaushalk@...cinc.com,
quic_tdas@...cinc.com, quic_tingweiz@...cinc.com,
quic_aiquny@...cinc.com, kernel@...cinc.com,
quic_bjorande@...cinc.com
Subject: Re: [PATCH 6/6] arm64: dts: qcom: add uart console support for SM4450
On 08/09/2023 08:58, Tengfei Fan wrote:
> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
> which helps SM4450 boot to shell with console on boards with this SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 14 +-
> arch/arm64/boot/dts/qcom/sm4450.dtsi | 258 ++++++++++++++++++++++++
> 2 files changed, 270 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> index 00a1c81ca397..bb8c58fb4267 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> @@ -10,9 +10,19 @@
> model = "Qualcomm Technologies, Inc. SM4450 QRD";
> compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>
> - aliases { };
> + aliases {
> + serial0 = &uart7;
> + };
>
> chosen {
> - bootargs = "console=hvc0";
> + stdout-path = "serial0:115200n8";
Wait, what? You told me you cannot use serial and stdout-path!
https://lore.kernel.org/all/f0f94ea9-94b1-ccd1-0a43-3cb119fc5d94@quicinc.com/
> };
> };
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index 2395b1d655a2..3af7255fca35 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -7,6 +7,8 @@
> #include <dt-bindings/clock/qcom,sm4450-gcc.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,sm4450.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> @@ -262,6 +264,26 @@
> };
> };
>
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm4450", "qcom,scm";
> + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
> + #reset-cells = <1>;
> + };
> + };
> +
> + clk_virt: interconnect-0 {
> + compatible = "qcom,sm4450-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect-1 {
> + compatible = "qcom,sm4450-mc-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> memory@...00000 {
> device_type = "memory";
> /* We expect the bootloader to fill in the size */
> @@ -387,12 +409,118 @@
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
> };
>
> + qupv3_id_0: geniqup@...000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x0 0x00ac0000 0x0 0x2000>;
> + ranges;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x163 0x0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
> + interconnect-names = "qup-core";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + uart7: serial@...000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0 0x00a88000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
> + status = "disabled";
> + };
> + };
> +
> + aggre1_noc: interconnect@...0000 {
> + tible = "qcom,sm4450-aggre1-noc";
> + reg = <0 0x016e0000 0 0x1c080>;
> + #interconnect-cells = <2>;
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect@...0000 {
> + compatible = "qcom,sm4450-aggre2-noc";
> + reg = <0 0x01700000 0 0x31080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + clocks = <&rpmhcc RPMH_IPA_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
> + };
> +
> + cnoc2: interconnect@...0000 {
Keep order by unit address.
> + compatible = "qcom,sm4450-cnoc2";
> + reg = <0 0x1500000 0 0x6200>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
...
> +
> intc: interrupt-controller@...00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> @@ -480,4 +711,31 @@
> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> };
> +
> + tlmm: pinctrl@...0000 {
You did not test it... This node cannot be here and tools will tell you
this. No need for review from us - tools are doing this.
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> + compatible = "qcom,sm4450-tlmm";
> + reg = <0 0x0f100000 0 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 137>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_rx: qup-uart7-rx-state {
> + pins = "gpio22";
> + function = "qup1_se2_l2";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + qup_uart7_tx: qup-uart7-tx-state {
> + pins = "gpio22";
> + function = "qup1_se2_l2";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> +
Stray blank line.
> };
Best regards,
Krzysztof
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