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Message-ID: <20230911164628.GA1295856-robh@kernel.org>
Date: Mon, 11 Sep 2023 11:46:28 -0500
From: Rob Herring <robh@...nel.org>
To: MD Danish Anwar <danishanwar@...com>
Cc: Andrew Lunn <andrew@...n.ch>, Roger Quadros <rogerq@...com>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paolo Abeni <pabeni@...hat.com>,
Jakub Kicinski <kuba@...nel.org>,
Eric Dumazet <edumazet@...gle.com>,
"David S. Miller" <davem@...emloft.net>,
Vignesh Raghavendra <vigneshr@...com>,
Simon Horman <horms@...nel.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, netdev@...r.kernel.org, srk@...com,
r-gunasekaran@...com, Roger Quadros <rogerq@...nel.org>
Subject: Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for
Half duplex support.
On Mon, Sep 11, 2023 at 11:31:59AM +0530, MD Danish Anwar wrote:
> In order to support half-duplex operation at 10M and 100M link speeds, the
> PHY collision detection signal (COL) should be routed to ICSSG
> GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal
> and apply the CSMA/CD algorithm applicable for half duplex operation. A DT
> property, "ti,half-duplex-capable" is introduced for this purpose. If
> board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can
> be added to eth node of ICSSG, MII port to support half duplex operation at
> that port.
>
> Reviewed-by: Roger Quadros <rogerq@...nel.org>
> Signed-off-by: MD Danish Anwar <danishanwar@...com>
> ---
> Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
> index 311c570165f9..bba17d4d5874 100644
> --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
> +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
> @@ -106,6 +106,13 @@ properties:
> phandle to system controller node and register offset
> to ICSSG control register for RGMII transmit delay
>
> + ti,half-duplex-capable:
> + type: boolean
> + description:
> + Enable half duplex operation on ICSSG MII port. This requires
Still have capable vs. enable confusion. Please reword the description.
> + PHY output pin (COL) to be routed to ICSSG GPIO pin
> + (PRGx_PRU0/1_GPIO10) as input.
> +
> required:
> - reg
> anyOf:
> --
> 2.34.1
>
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