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Message-ID: <1694429639-21484-14-git-send-email-quic_mojha@quicinc.com>
Date: Mon, 11 Sep 2023 16:23:55 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: <corbet@....net>, <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<keescook@...omium.org>, <tony.luck@...el.com>,
<gpiccoli@...lia.com>, <mathieu.poirier@...aro.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<linus.walleij@...aro.org>, <andy.shevchenko@...il.com>,
<vigneshr@...com>, <nm@...com>, <matthias.bgg@...il.com>,
<kgene@...nel.org>, <alim.akhtar@...sung.com>,
<bmasney@...hat.com>, <quic_tsoni@...cinc.com>
CC: <linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-hardening@...r.kernel.org>,
<linux-remoteproc@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-gpio@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<linux-samsung-soc@...r.kernel.org>, <kernel@...cinc.com>,
<quic_mojha@...cinc.com>
Subject: [REBASE PATCH v5 13/17] firmware: qcom_scm: provide a read-modify-write function
It was realized by Srinivas K. that there is a need of
read-modify-write scm exported function so that it can
be used by multiple clients.
Let's introduce qcom_scm_io_update_field() which masks
out the bits and write the passed value to that
bit-offset. Subsequent patch will use this function.
Suggested-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Signed-off-by: Mukesh Ojha <quic_mojha@...cinc.com>
Tested-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com> # IPQ9574 and IPQ5332
---
drivers/firmware/qcom_scm.c | 20 ++++++++++++++++++++
include/linux/firmware/qcom/qcom_scm.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 06fe8aca870d..321133f0950d 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -74,6 +74,7 @@ static const char * const qcom_scm_convention_names[] = {
};
static struct qcom_scm *__scm;
+static DEFINE_SPINLOCK(lock);
static int qcom_scm_clk_enable(void)
{
@@ -403,6 +404,25 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
}
EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
+int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, unsigned int val)
+{
+ unsigned int old, new;
+ int ret;
+
+ spin_lock(&lock);
+ ret = qcom_scm_io_readl(addr, &old);
+ if (ret)
+ goto unlock;
+
+ new = (old & ~mask) | (val & mask);
+
+ ret = qcom_scm_io_writel(addr, new);
+unlock:
+ spin_unlock(&lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_scm_io_update_field);
+
static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
struct qcom_scm_desc desc = {
diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
index 0c091a3f6d49..eb750286abb6 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -84,6 +84,8 @@ extern bool qcom_scm_pas_supported(u32 peripheral);
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
+extern int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask,
+ unsigned int val);
extern bool qcom_scm_restore_sec_cfg_available(void);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
--
2.7.4
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