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Message-ID: <20230911074233.31556-10-shawn.sung@mediatek.com>
Date: Mon, 11 Sep 2023 15:42:22 +0800
From: Hsiao Chien Sung <shawn.sung@...iatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
"CK Hu" <ck.hu@...iatek.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>
CC: Conor Dooley <conor+dt@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
NĂcolas F . R . A . Prado
<nfraprado@...labora.com>, Philipp Zabel <p.zabel@...gutronix.de>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<dri-devel@...ts.freedesktop.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Singo Chang <singo.chang@...iatek.com>,
"Nancy . Lin" <nancy.lin@...iatek.com>,
"Jason-JH . Lin" <jason-jh.lin@...iatek.com>,
Hsiao Chien Sung <shawn.sung@...iatek.com>
Subject: [RESEND PATCH v6 09/20] soc: mediatek: Support reset bit mapping in mmsys driver
- Reset ID must starts from 0 and be consecutive, but
the reset bits in our hardware design is not continuous,
some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@...iatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
drivers/soc/mediatek/mtk-mmsys.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 84b2d8187011..6fc59f85f4fa 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -310,6 +310,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
u32 offset;
u32 reg;
+ if (mmsys->data->rst_tb) {
+ if (id >= mmsys->data->num_resets) {
+ dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+ id, mmsys->data->num_resets);
+ return -EINVAL;
+ }
+ id = mmsys->data->rst_tb[id];
+ }
+
offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
id = id % MMSYS_SW_RESET_PER_REG;
reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 964b5449d672..dfbb742eaa11 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,6 +78,8 @@
#define DSI_SEL_IN_RDMA 0x1
#define DSI_SEL_IN_MASK 0x1
+#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
+
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
+ const u8 *rst_tb;
const u32 num_resets;
const bool is_vppsys;
const u8 vsync_len;
--
2.18.0
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