linux-kernel - Re: [PATCH v2] drm/msm/dpu: change _dpu_plane_calc

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Date:   Mon, 11 Sep 2023 12:54:17 +0200
From:   Nia Espera <nespera@...lia.com>
To:     Abhinav Kumar <quic_abhinavk@...cinc.com>,
        freedreno@...ts.freedesktop.org, Rob Clark <robdclark@...il.com>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Sean Paul <sean@...rly.run>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Kalyan Thota <quic_kalyant@...cinc.com>
Cc:     dri-devel@...ts.freedesktop.org, quic_jesszhan@...cinc.com,
        quic_parellan@...cinc.com, Rob Clark <robdclark@...omium.org>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] drm/msm/dpu: change _dpu_plane_calc_bw() to use u64 to
 avoid overflow

On 9/8/23 03:26, Abhinav Kumar wrote:
> _dpu_plane_calc_bw() uses integer variables to calculate the bandwidth
> used during plane bandwidth calculations. However for high resolution
> displays this overflows easily and leads to below errors
>
> [dpu error]crtc83 failed performance check -7
>
> Promote the intermediate variables to u64 to avoid overflow.
>
> changes in v2:
> 	- change to u64 where actually needed in the math
>
> Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for display")
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/32
> Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
Reported-by: Nia Espera <nespera@...lia.com>
Tested-by: Nia Espera <nespera@...lia.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c2aaaded07ed..98c1b22e9bca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -119,6 +119,7 @@ static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
>   	struct dpu_sw_pipe_cfg *pipe_cfg)
>   {
>   	int src_width, src_height, dst_height, fps;
> +	u64 plane_pixel_rate, plane_bit_rate;
>   	u64 plane_prefill_bw;
>   	u64 plane_bw;
>   	u32 hw_latency_lines;
> @@ -136,13 +137,12 @@ static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
>   	scale_factor = src_height > dst_height ?
>   		mult_frac(src_height, 1, dst_height) : 1;
>   
> -	plane_bw =
> -		src_width * mode->vtotal * fps * fmt->bpp *
> -		scale_factor;
> +	plane_pixel_rate = src_width * mode->vtotal * fps;
> +	plane_bit_rate = plane_pixel_rate * fmt->bpp;
>   
> -	plane_prefill_bw =
> -		src_width * hw_latency_lines * fps * fmt->bpp *
> -		scale_factor * mode->vtotal;
> +	plane_bw = plane_bit_rate * scale_factor;
> +
> +	plane_prefill_bw = plane_bw * hw_latency_lines;
>   
>   	if ((vbp+vpw) > hw_latency_lines)
>   		do_div(plane_prefill_bw, (vbp+vpw));