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Message-ID: <04eb9f71-78f0-41f2-96a6-fc759ba296fa@linaro.org>
Date: Mon, 11 Sep 2023 16:15:10 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
vireshk@...nel.org, nm@...com, sboyd@...nel.org,
myungjoo.ham@...sung.com, kyungmin.park@...sung.com,
cw00.choi@...sung.com, andersson@...nel.org,
konrad.dybcio@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
jejb@...ux.ibm.com, martin.petersen@...cle.com
Cc: alim.akhtar@...sung.com, avri.altman@....com, bvanassche@....org,
linux-scsi@...r.kernel.org, linux-pm@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
quic_asutoshd@...cinc.com, quic_cang@...cinc.com,
quic_nitirawa@...cinc.com, quic_narepall@...cinc.com,
quic_bhaskarv@...cinc.com, quic_richardp@...cinc.com,
quic_nguyenb@...cinc.com, quic_ziqichen@...cinc.com,
bmasney@...hat.com, krzysztof.kozlowski@...aro.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: sdm845: Add OPP table support to
UFSHC
On 31/07/2023 19:33, Manivannan Sadhasivam wrote:
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> UFS host controller, when scaling gears, should choose appropriate
> performance state of RPMh power domain controller along with clock
> frequency. So let's add the OPP table support to specify both clock
> frequency and RPMh performance states replacing the old "freq-table-hz"
> property.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> [mani: Splitted pd change and used rpmhpd_opp_low_svs]
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++++++++++++++++++++-------
> 1 file changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 055ca80c0075..2ea6eb44953e 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -2605,22 +2605,44 @@ ufs_mem_hc: ufshc@...4000 {
> <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
> <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> - freq-table-hz =
> - <50000000 200000000>,
> - <0 0>,
> - <0 0>,
> - <37500000 150000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>,
> - <0 0>,
> - <75000000 300000000>;
> +
> + operating-points-v2 = <&ufs_opp_table>;
>
> interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
> <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> interconnect-names = "ufs-ddr", "cpu-ufs";
>
> status = "disabled";
> +
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-50000000 {
> + opp-hz = /bits/ 64 <50000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <37500000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
I'd say, I'm still slightly unhappy about the 0 clock rates here.
We need only three clocks here: core, core_clk_unipro and optional
ice_core_clk. Can we modify ufshcd_parse_operating_points() to pass only
these two or three clock names to devm_pm_opp_set_config() ? The OPP
core doesn't need to know about all the rest of the clocks.
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <150000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> };
>
> ufs_mem_phy: phy@...7000 {
--
With best wishes
Dmitry
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