linux-kernel - Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata

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Message-ID: <ZP59wF5Knq3G7On_@APC323>
Date:   Mon, 11 Sep 2023 10:38:56 +0800
From:   Yu-Chien Peter Lin <peterlin@...estech.com>
To:     Samuel Holland <samuel.holland@...ive.com>
CC:     <ajones@...tanamicro.com>, <heiko@...ech.de>,
        <samuel@...lland.org>, <geert+renesas@...der.be>,
        <n.shubin@...ro.com>, <dminus@...estech.com>,
        <ycliang@...estech.com>, <tim609@...estech.com>,
        <locus84@...estech.com>, <dylan@...estech.com>,
        <linux-riscv@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
        <paul.walmsley@...ive.com>, <palmer@...belt.com>,
        <aou@...s.berkeley.edu>, <conor.dooley@...rochip.com>,
        <atishp@...shpatra.org>, <anup@...infault.org>,
        <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata

Hi Samuel,

On Wed, Sep 06, 2023 at 09:48:35PM -0500, Samuel Holland wrote:
> If the code here needs to be different, then it must check that it is actually
> running on an Andes core, not just that the errata Kconfig option is enabled.

Thank you for catching this, will fix in PATCH v2.

> However, I suggest setting riscv_pmu_irq_num to the real IRQ number:
>   riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU;
> and then adding a new variable for the mask:
>   riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
> which handles the large IRQ number somewhat more generically, and reduces the
> number of bit operations needed elsewhere in the driver.

I will make changes according to your suggestions. Thank you!

> Or we could use IRQ chip operations here instead of direct CSR acccess. But
> maybe the direct CSR access is needed for performance?
> 
> Regards,
> Samuel

Best regards,
Peter Lin