linux-kernel - [PATCH] drm/panel: boe-tv101wum-nl6: Completely Pull GPW to VGL before TP term

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Date:   Tue, 12 Sep 2023 18:59:32 +0800
From:   Ruihai Zhou <zhouruihai@...qin.corp-partner.google.com>
To:     neil.armstrong@...aro.org, quic_jesszhan@...cinc.com,
        sam@...nborg.org, airlied@...il.com, daniel@...ll.ch
Cc:     dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        linus.walleij@...aro.org,
        Ruihai Zhou <zhouruihai@...qin.corp-partner.google.com>
Subject: [PATCH] drm/panel: boe-tv101wum-nl6: Completely Pull GPW to VGL before TP term

The sta_himax83102 panel sometimes shows abnormally flickering
horizontal lines. The front gate output will precharge the X point of
the next pole circuit before TP(TouchPanel Enable) term starts, and wait
until the end of the TP term to resume the CLK. For this reason, the X
point must be maintained during the TP term. In abnormal case, we
measured a slight leakage at point X. This because during the TP term,
the GPW does not fully pull the VGL low, causing the TFT to not be
closed tightly.

To fix this, we completely pull GPW to VGL before entering the TP term.
This will ensure that the TFT is closed tightly and prevent the abnormal
display.

Signed-off-by: Ruihai Zhou <zhouruihai@...qin.corp-partner.google.com>
---
This patch base on original fixes series [1]
[1] https://patchwork.kernel.org/project/dri-devel/cover/20230703-fix-boe-tv101wum-nl6-v3-0-bd6e9432c755@linaro.org/
---
 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index c2ee2c6b4150..e37b9b4f528d 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -1305,9 +1305,8 @@ static int starry_himax83102_j02_init(struct mipi_dsi_device *dsi)
 	mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x01, 0xBF, 0x11);
 	mipi_dsi_dcs_write_seq(dsi, 0xCB, 0x86);
 	mipi_dsi_dcs_write_seq(dsi, 0xD2, 0x3C, 0xFA);
-	mipi_dsi_dcs_write_seq(dsi, 0xE9, 0xC5);
-	mipi_dsi_dcs_write_seq(dsi, 0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01);
-	mipi_dsi_dcs_write_seq(dsi, 0xE9, 0x3F);
+	mipi_dsi_dcs_write_seq(dsi, 0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+			       0x0C, 0x01);
 	mipi_dsi_dcs_write_seq(dsi, 0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0,
 			       0x00, 0x00, 0x20, 0x40, 0x50, 0x40);
 	mipi_dsi_dcs_write_seq(dsi, 0xBD, 0x02);
-- 
2.17.1