linux-kernel - Re: [PATCH 20/37] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <169453454306.864438.17337946061239259164.robh@kernel.org>
Date:   Tue, 12 Sep 2023 11:02:23 -0500
From:   Rob Herring <robh@...nel.org>
To:     Claudiu <claudiu.beznea@...on.dev>
Cc:     ulf.hansson@...aro.org, arnd@...db.de, gregkh@...uxfoundation.org,
        wsa+renesas@...g-engineering.com, linux-kernel@...r.kernel.org,
        linus.walleij@...aro.org, linux-renesas-soc@...r.kernel.org,
        robh+dt@...nel.org, prabhakar.mahadev-lad.rj@...renesas.com,
        nfraprado@...labora.com, krzysztof.kozlowski+dt@...aro.org,
        linux-mmc@...r.kernel.org, neil.armstrong@...aro.org,
        rafal@...ecki.pl, linux-arm-kernel@...ts.infradead.org,
        conor+dt@...nel.org, mturquette@...libre.com,
        biju.das.jz@...renesas.com, linux-serial@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea.uj@...renesas.com>,
        magnus.damm@...il.com, sboyd@...nel.org, quic_bjorande@...cinc.com,
        catalin.marinas@....com, konrad.dybcio@...aro.org,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        will@...nel.org, geert+renesas@...der.be, jirislaby@...nel.org,
        linux-gpio@...r.kernel.org
Subject: Re: [PATCH 20/37] dt-bindings: clock: renesas,rzg2l-cpg: document
 RZ/G3S SoC


On Tue, 12 Sep 2023 07:51:40 +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> Add documentation for RZ/G3S CPG. RZ/G3S CPG module is almost identical
> with the one available in RZ/G2{L, UL} the exception being some core
> clocks as follows:
> - SD clock is composed by a mux and a divider and the divider
>   has some limitation (div = 1 cannot be set if mux rate is 800MHz).
> - there are 3 SD clocks
> - OCTA and TSU clocks are specific to RZ/G3S
> - PLL1/4/6 are specific to RZ/G3S with its own computation formula
> Even with this RZ/G3S could use the same bindings as RZ/G2L.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>  Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@...nel.org>