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Message-ID: <8490f909-c0ad-5a6d-7a97-03c80a8b47ba@omp.ru>
Date:   Tue, 12 Sep 2023 19:43:52 +0300
From:   Sergey Shtylyov <s.shtylyov@....ru>
To:     Claudiu <claudiu.beznea@...on.dev>, <geert+renesas@...der.be>,
        <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>, <ulf.hansson@...aro.org>,
        <linus.walleij@...aro.org>, <gregkh@...uxfoundation.org>,
        <jirislaby@...nel.org>, <magnus.damm@...il.com>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <prabhakar.mahadev-lad.rj@...renesas.com>,
        <biju.das.jz@...renesas.com>, <quic_bjorande@...cinc.com>,
        <arnd@...db.de>, <konrad.dybcio@...aro.org>,
        <neil.armstrong@...aro.org>, <nfraprado@...labora.com>,
        <rafal@...ecki.pl>, <wsa+renesas@...g-engineering.com>
CC:     <linux-renesas-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-mmc@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
        <linux-serial@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 08/37] clk: renesas: rzg2l: trust value returned by
 hardware

On 9/12/23 7:51 AM, Claudiu wrote:

> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> Initial value of CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. Hardware user's
> manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is
> prohibited. The rzg2l_cpg_sd_clk_mux_get_parent() should just read
> CPG_PL2SDHI_DSEL, trust the value and return the proper clock parent index
> based on the read value. Do this.
> 
> Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>  drivers/clk/renesas/rzg2l-cpg.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index 1195d4b1f545..d0d086d6dc51 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -239,14 +239,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
>  
>  	val >>= GET_SHIFT(hwdata->conf);
>  	val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
> -	if (val) {
> -		val--;
> -	} else {
> -		/* Prohibited clk source, change it to 533 MHz(reset value) */
> -		rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);
> -	}
>  
> -	return val;
> +	return val ? --val : val;

	return val ? val - 1 : 0;

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