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Message-Id: <20230912045157.177966-10-claudiu.beznea.uj@bp.renesas.com>
Date: Tue, 12 Sep 2023 07:51:29 +0300
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be, mturquette@...libre.com, sboyd@...nel.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, ulf.hansson@...aro.org,
linus.walleij@...aro.org, gregkh@...uxfoundation.org,
jirislaby@...nel.org, magnus.damm@...il.com,
catalin.marinas@....com, will@...nel.org,
prabhakar.mahadev-lad.rj@...renesas.com,
biju.das.jz@...renesas.com, quic_bjorande@...cinc.com,
arnd@...db.de, konrad.dybcio@...aro.org, neil.armstrong@...aro.org,
nfraprado@...labora.com, rafal@...ecki.pl,
wsa+renesas@...g-engineering.com
Cc: linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH 09/37] clk: renesas: rzg2l: fix computation formula
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
According to hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf)
the computation formula for PLL rate is as follows:
Fout = ((m + k/65536) * Fin) / (p * 2^s)
and k has values in range [-32768, 32767]. Dividing k by 65536 with
integer variables leads all the time to zero. Thus we may have slight
differences b/w what has been set vs. what is displayed. Thus,
get rid of this and decompose the formula before dividing k by 65536.
Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index d0d086d6dc51..b391c9548421 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -696,18 +696,22 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
struct pll_clk *pll_clk = to_pll(hw);
struct rzg2l_cpg_priv *priv = pll_clk->priv;
unsigned int val1, val2;
- unsigned int mult = 1;
- unsigned int div = 1;
+ unsigned int div;
+ u64 rate;
+ s16 kdiv;
if (pll_clk->type != CLK_TYPE_SAM_PLL)
return parent_rate;
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
- mult = MDIV(val1) + KDIV(val1) / 65536;
+ kdiv = KDIV(val1);
div = PDIV(val1) << SDIV(val2);
- return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
+ rate = (u64)MDIV(val1) * parent_rate;
+ rate += ((long long)parent_rate * kdiv) / 65536;
+
+ return DIV_ROUND_CLOSEST_ULL(rate, div);
}
static const struct clk_ops rzg2l_cpg_pll_ops = {
--
2.39.2
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