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Message-Id: <20230912072232.2455-1-jszhang@kernel.org>
Date: Tue, 12 Sep 2023 15:22:32 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Drew Fustini <dfustini@...libre.com>
Subject: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
Tested-by: Drew Fustini <dfustini@...libre.com>
---
Since v1:
- rebase on v6.6-rc1
- collect Tested-by tag
arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..ff364709a6df 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
+ dma-noncoherent;
ranges;
plic: interrupt-controller@...8000000 {
--
2.40.1
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