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Message-ID: <20230912092300.GI603@alberich>
Date: Tue, 12 Sep 2023 11:23:00 +0200
From: Andreas Herrmann <aherrmann@...e.de>
To: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
Cc: x86@...nel.org, Andreas Herrmann <aherrmann@...e.com>,
Catalin Marinas <catalin.marinas@....com>,
Chen Yu <yu.c.chen@...el.com>, Len Brown <len.brown@...el.com>,
Radu Rendec <rrendec@...hat.com>,
Pierre Gondois <Pierre.Gondois@....com>,
Pu Wen <puwen@...on.cn>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
Sudeep Holla <sudeep.holla@....com>,
Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
Will Deacon <will@...nel.org>, Zhang Rui <rui.zhang@...el.com>,
stable@...r.kernel.org, Ricardo Neri <ricardo.neri@...el.com>,
"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/3] x86/cacheinfo: Set the number of leaves per CPU
On Mon, Sep 11, 2023 at 08:23:50PM -0700, Ricardo Neri wrote:
> Hi Andreas,
>
> Agreed. Testing is important. For the specific case of these patches, I
> booted CONFIG_PREEMPT_RT and !CONFIG_PREEMPT_RT kernels. Then I
> a) Ensured that the splat reported in commit 5944ce092b97
> ("arch_topology: Build cacheinfo from primary CPU") was not observed.
>
> b) Ensured that /sys/devices/system/cpu/cpuX/cache is present.
>
> c) Ensured that the contents /sys/devices/system/cpu/cpuX/cache is the
> same before and after my patches.
>
> I tested on the following systems: Intel Alder Lake, Intel Meteor
> Lake, 2-socket Intel Icelake server, 2-socket Intel Cascade Lake server,
> 2-socket Intel Skylake server, 4-socket Intel Broadwell server, 2-socket
> Intel Haswell server, 2-socket AMD Rome server, and 2-socket AMD Milan
> server.
>
> Thanks and BR,
> Ricardo
Thanks for all the tests and info.
--
Regards,
Andreas
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nürnberg, Germany
GF: Ivo Totev, Andrew McDonald, Werner Knoblich
(HRB 36809, AG Nürnberg)
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