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Message-ID: <20230914093027.3901602-1-w.egorov@phytec.de>
Date: Thu, 14 Sep 2023 11:30:27 +0200
From: Wadim Egorov <w.egorov@...tec.de>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>
CC: <upstream@...ts.phytec.de>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH] arm64: dts: ti: phycore-am64: Add RTC interrupt pin
Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device
tree if available") we can now use the interrupt pin of the RTC.
Let's add interrupt pin definitions to the SoM RTC.
Signed-off-by: Wadim Egorov <w.egorov@...tec.de>
---
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 1c2c8f0daca9..f87f09d83c95 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -126,6 +126,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
};
+
+ rtc_pins_default: rtc-defaults-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
+ >;
+ };
};
&cpsw3g {
@@ -177,6 +183,11 @@ eeprom@50 {
i2c_som_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_pins_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
};
};
--
2.25.1
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