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Message-ID: <20230914-2232dea1c6d03fb5985755e6@orel>
Date: Thu, 14 Sep 2023 12:15:50 +0200
From: Andrew Jones <ajones@...tanamicro.com>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Haibo Xu <haibo1.xu@...el.com>, xiaobo55x@...il.com,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Paolo Bonzini <pbonzini@...hat.com>,
Shuah Khan <shuah@...nel.org>, Marc Zyngier <maz@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Sean Christopherson <seanjc@...gle.com>,
Ricardo Koller <ricarkol@...gle.com>,
Vishal Annapurve <vannapurve@...gle.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Vipin Sharma <vipinsh@...gle.com>,
David Matlack <dmatlack@...gle.com>,
Colton Lewis <coltonlewis@...gle.com>,
Aaron Lewis <aaronlewis@...gle.com>,
Thomas Huth <thuth@...hat.com>, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, kvm@...r.kernel.org,
linux-kselftest@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.linux.dev,
kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 9/9] KVM: riscv: selftests: Add sstc timer test
On Thu, Sep 14, 2023 at 10:52:15AM +0100, Conor Dooley wrote:
> On Thu, Sep 14, 2023 at 11:36:01AM +0200, Andrew Jones wrote:
> > > +static inline void cpu_relax(void)
> > > +{
> > > +#ifdef __riscv_zihintpause
> > > + asm volatile("pause" ::: "memory");
> > > +#else
> > > + /* Encoding of the pause instruction */
> > > + asm volatile(".4byte 0x100000F" ::: "memory");
> > > +#endif
> > > +}
> >
> > cpu_relax() should go to include/riscv/processor.h
>
> Can the one from asm/vdso/processor.h be reused, or are there special
> considerations preventing that?
We'd need to copy it into tools/arch/riscv/include/asm, but it could be
done. Hmm, now that I look at it, I see we're missing the barrier() call
in this kvm selftests version.
Thanks,
drew
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