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Message-ID: <d54e14b2-9897-fbd4-7f5f-f5dd44c40f5e@tuxon.dev>
Date: Fri, 15 Sep 2023 08:47:42 +0300
From: claudiu beznea <claudiu.beznea@...on.dev>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
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Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 10/37] clk: renesas: rzg2l: use core->name for clock name
On 14.09.2023 16:04, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@...on.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>>
>> core->name already contains the clock name thus, there is no
>> need to check the GET_SHIFT(core->conf) to decide on it.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -266,7 +266,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
>> clk_hw_data->priv = priv;
>> clk_hw_data->conf = core->conf;
>>
>> - init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
>> + init.name = core->name;
>
> Note that this does change the case of the names (e.g. "SD0" => "sd0").
> I guess no one cares...
As of my experiments and investigation we should be good with it.
>
>> init.ops = &rzg2l_cpg_sd_clk_mux_ops;
>> init.flags = 0;
>> init.num_parents = core->num_parents;
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
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