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Message-Id: <20230915072333.117991-1-wangchen20@iscas.ac.cn>
Date:   Fri, 15 Sep 2023 15:23:33 +0800
From:   Wang Chen <unicornxw@...il.com>
To:     linux-riscv@...ts.infradead.org, conor@...nel.org,
        aou@...s.berkeley.edu, krzysztof.kozlowski+dt@...aro.org,
        palmer@...belt.com, paul.walmsley@...ive.com, robh+dt@...nel.org
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        jszhang@...nel.org, guoren@...nel.org, chao.wei@...hgo.com,
        xiaoguang.xing@...hgo.com, Wang Chen <wangchen20@...as.ac.cn>
Subject: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles

The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Signed-off-by: Wang Chen <wangchen20@...as.ac.cn>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@...hgo.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:
-- 
2.25.1

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