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Message-ID: <80e36ff513504a0382a1cbce83e42295@huawei.com>
Date: Fri, 15 Sep 2023 09:34:46 +0000
From: Salil Mehta <salil.mehta@...wei.com>
To: "Rafael J. Wysocki" <rafael@...nel.org>,
"Russell King (Oracle)" <linux@...linux.org.uk>
CC: Ard Biesheuvel <ardb@...nel.org>,
Jonathan Cameron <jonathan.cameron@...wei.com>,
James Morse <james.morse@....com>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
"loongarch@...ts.linux.dev" <loongarch@...ts.linux.dev>,
"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"kvmarm@...ts.linux.dev" <kvmarm@...ts.linux.dev>,
"x86@...nel.org" <x86@...nel.org>,
"Jean-Philippe Brucker" <jean-philippe@...aro.org>,
"jianyong.wu@....com" <jianyong.wu@....com>,
"justin.he@....com" <justin.he@....com>
Subject: RE: [RFC PATCH v2 27/35] ACPICA: Add new MADT GICC flags fields [code
first?]
> From: Rafael J. Wysocki <rafael@...nel.org>
> Sent: Friday, September 15, 2023 9:45 AM
> To: Russell King (Oracle) <linux@...linux.org.uk>
> Cc: Salil Mehta <salil.mehta@...wei.com>; Ard Biesheuvel <ardb@...nel.org>;
> Jonathan Cameron <jonathan.cameron@...wei.com>; James Morse
> <james.morse@....com>; linux-pm@...r.kernel.org; loongarch@...ts.linux.dev;
> linux-acpi@...r.kernel.org; linux-arch@...r.kernel.org; linux-
> kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> riscv@...ts.infradead.org; kvmarm@...ts.linux.dev; x86@...nel.org; Jean-
> Philippe Brucker <jean-philippe@...aro.org>; jianyong.wu@....com;
> justin.he@....com
> Subject: Re: [RFC PATCH v2 27/35] ACPICA: Add new MADT GICC flags fields
> [code first?]
>
> On Fri, Sep 15, 2023 at 9:09 AM Russell King (Oracle)
> <linux@...linux.org.uk> wrote:
> >
> > On Fri, Sep 15, 2023 at 02:29:13AM +0000, Salil Mehta wrote:
> > > On x86, during init, if the MADT entry for LAPIC is found to be
> > > online-capable and is enabled as well then possible and present
> >
> > Note that the ACPI spec says enabled + online-capable isn't defined.
> >
> > "The information conveyed by this bit depends on the value of the
> > Enabled bit. If the Enabled bit is set, this bit is reserved and
> > must be zero."
> >
> > So, if x86 is doing something with the enabled && online-capable
> > state (other than ignoring the online-capable) then technically it
> > is doing something that the spec doesn't define
>
> And so it is wrong.
Or maybe, specification has not been updated yet. code-first?
>
> > - and it's
> > completely fine if aarch64 does something else (maybe treating it
> > strictly as per the spec and ignoring online-capable.)
>
> That actually is the only compliant thing that can be done.
Yes, but the question is it what is required and does it solves
the problem of Hotplug. I think no.
By complying with what is there in the spec means we have to
do the tradeoff between having not to support hot(un)plugging
of the cold-plugged CPUs Vs risk of breaking the legacy OS
attempting to use newer platforms with Hotplug support. Later
is more of a ARM problem as we are not allowed to tweak the
ACPI tables once the system has booted.
>
> As per the spec (quoted above), a platform firmware setting
> online-capable to 1 when Enabled is set is not compliant and it is
> invalid to treat this as meaningful data.
Correct. but is it really what we need? We need both of the
Bits to be set for supporting hot(un)plugging of cold booted
CPUs.
>
> As currently defined, online-capable is only applicable to CPUs that
> are not enabled to start with and its role is to make it clear whether
> or not they can be enabled later AFAICS.
Correct.
>
> If there is a need to represent the case in which a CPI that is
> enabled to start with can be disabled, but cannot be enabled again,
> the spec needs to be updated.
Absolutely. And that’s what my humble suggestion is as well.
Thanks
Salil.
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