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Message-ID: <CAMuHMdWc6yy=oJDo4zMdvB-t8pjCuE1oJ_Y6Ck0aX_hPkfhPug@mail.gmail.com>
Date: Fri, 15 Sep 2023 13:59:42 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
ulf.hansson@...aro.org, linus.walleij@...aro.org,
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Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and
resets definitions
On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Add RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module
> clocks and resets.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a08g045-cpg.h
> +/* R9A08G045 Module Clocks */
> +#define R9A08G045_USB_U2H0_HCLK 65
> +#define R9A08G045_USB_U2H1_HCLK 66
> +#define R9A08G045_USB_U2P_EXR_CPUCLK 67
> +#define R9A08G045_USB_PCLK 68
> +#define R9A08G045_USB_SCLK 69
There is no USB_SCLK bit in CPG_CLKON_USB, so please drop
R9A08G045_USB_SCLK.
> +/* R9A08G045 Resets */
> +#define R9A08G045_SRAM_ACPU_ARESETN0 11
> +#define R9A08G045_SRAM_ACPU_ARESETN1 12
> +#define R9A08G045_SRAM_ACPU_ARESETN2 13
There is no SRAM_ACPU_ARESETN2 bit in CPG_RST_SRAM_MCPU,
so please drop R9A08G045_SRAM_ACPU_ARESETN2.
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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