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Message-ID: <650553545372e_d7cc829461@dwillia2-xfh.jf.intel.com.notmuch>
Date: Sat, 16 Sep 2023 00:03:48 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: Ira Weiny <ira.weiny@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Dave Jiang <dave.jiang@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Ira Weiny <ira.weiny@...el.com>
Subject: RE: [PATCH 3/3] tools/testing/cxl: Document test configurations
Ira Weiny wrote:
> The devices created, their relationship, and intended testing purpose is
> not extremely clear, especially for those unfamiliar with cxl-test.
>
> Document the purpose of each hierarchy. Add ASCII art to show the
> relationship of devices. Group the device declarations together based
> on the hierarchies.
>
> Signed-off-by: Ira Weiny <ira.weiny@...el.com>
> ---
> tools/testing/cxl/test/cxl.c | 75 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index bf00dc52fe96..bd38a5fb60ae 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -23,6 +23,31 @@ static int interleave_arithmetic;
> #define NR_CXL_PORT_DECODERS 8
> #define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH)
>
> +/*
> + * Interleave testing
> + *
> + * +---------------+ +---------------+
> + * | host_bridge[0]| | host_bridge[1]|
> + * +-/---------\---+ +--/---------\--+
> + * /- -\ /- -\
> + * /- -\ /- -\
> + * +-------------+ +-------------+ +-------------+ +-------------+
> + * |root_port[0] | |root_port[1] | |root_port[2] | |root_port[3] |
> + * +------|------+ +------|------+ +------|------+ +------|------+
> + * | | | |
> + * +-------|-------+ +-------|-------+ +-------|-------+ +-------|-------+
> + * |switch_uport[0]| |switch_uport[1]| |switch_uport[2]| |switch_uport[3]|
> + * +---|-------|---+ +---/-------|---+ +---/-------|---+ +---|-------\---+
> + * | \ / \ / \ / \
> + * +----|----++--|------++---------++----|----++---------++----|----++----|----++---------+
> + * |switch ||switch ||switch ||switch ||switch ||switch ||switch ||switch |
> + * |_dport[0]||_dport[1]||_dport[2]||_dport[3]||_dport[4]||_dport[5]||_dport[6]||_dport[7]|
> + * +----|----++--|------++----|----++----|----++----|----++----|----++----|----++----|----+
> + * | | | | | | | |
> + * +---|--+ +-|----+ +---|--+ +---|--+ +--|---+ +---|--+ +---|--+ +---|--+
> + * |mem[0]| |mem[1]| |mem[2]| |mem[3]| |mem[4]| |mem[5]| |mem[6]| |mem[7]|
> + * +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+
> + */
Circling back to merge this I realize that the numbering is off. For
example a snippet from "cxl list -BPT -b cxl_test"
"ports:root3":[
{
"port":"port5",
"host":"cxl_host_bridge.1",
"depth":1,
"nr_dports":2,
"dports":[
{
"dport":"cxl_root_port.1",
"id":1
},
{
"dport":"cxl_root_port.3",
"id":3
}
],
This is due to the modulo math at setup time. I only noticed this
because I wanted a diagram to refer to when doing some recent
extensions.
I wonder if we could just use "cxl list" to maintain this diagram, or
maybe circle back and use this to keep an image up to date on a web page
somewhere:
https://lore.kernel.org/linux-cxl/cover.1660895649.git.sunfishho12@gmail.com/
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