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Message-Id: <20230916-saddling-dastardly-8cf6d1263c24@spud>
Date:   Sat, 16 Sep 2023 10:14:00 +0100
From:   Conor Dooley <conor@...nel.org>
To:     linux-riscv@...ts.infradead.org
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Samuel Holland <samuel@...lland.org>,
        devicetree@...r.kernel.org, linux-sunxi@...ts.linux.dev,
        linux-kernel@...r.kernel.org
Subject: [PATCH v1] riscv: dts: allwinner: remove address-cells from intc node

From: Conor Dooley <conor.dooley@...rochip.com>

A recent submission [1] from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus, highlighting that
the D1 DT has been incorrectly using #address-cells since its
introduction. It has no child nodes, so #address-cells is not needed.
Remove it.

Fixes: 077e5f4f5528 ("riscv: dts: allwinner: Add the D1/D1s SoC devicetree")
Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
CC: Rob Herring <robh+dt@...nel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Conor Dooley <conor+dt@...nel.org>
CC: Chen-Yu Tsai <wens@...e.org>
CC: Jernej Skrabec <jernej.skrabec@...il.com>
CC: Samuel Holland <samuel@...lland.org>
CC: devicetree@...r.kernel.org
CC: linux-riscv@...ts.infradead.org
CC: linux-sunxi@...ts.linux.dev
CC: linux-kernel@...r.kernel.org
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 8275630af977..b8684312593e 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -30,7 +30,6 @@ cpu0: cpu@0 {
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
-				#address-cells = <0>;
 				#interrupt-cells = <1>;
 			};
 		};
-- 
2.39.2

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