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Message-ID: <CAMuHMdWcfK0GjKsho5+SOQT0mk9pRXTfPgu2rc-peAM2yeiV-Q@mail.gmail.com>
Date: Mon, 18 Sep 2023 09:00:16 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: claudiu beznea <claudiu.beznea@...on.dev>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
ulf.hansson@...aro.org, linus.walleij@...aro.org,
gregkh@...uxfoundation.org, jirislaby@...nel.org,
magnus.damm@...il.com, catalin.marinas@....com, will@...nel.org,
prabhakar.mahadev-lad.rj@...renesas.com,
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arnd@...db.de, konrad.dybcio@...aro.org, neil.armstrong@...aro.org,
nfraprado@...labora.com, rafal@...ecki.pl,
wsa+renesas@...g-engineering.com,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 22/37] clk: renesas: add minimal boot support for RZ/G3S SoC
Hi Claudiu,
On Mon, Sep 18, 2023 at 8:20 AM claudiu beznea <claudiu.beznea@...on.dev> wrote:
> On 15.09.2023 15:52, Geert Uytterhoeven wrote:
> > On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >>
> >> Add minimal clock and reset support for RZ/G3S SoC to be able to boot
> >> Linux from SD Card/eMMC. This includes necessary core clocks for booting
> >> and GIC, SCIF, GPIO, SD0 mod clocks and resets.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- /dev/null
> >> +++ b/drivers/clk/renesas/r9a08g045-cpg.c
> >> @@ -0,0 +1,217 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * RZ/G3S CPG driver
> >> + *
> >> + * Copyright (C) 2023 Renesas Electronics Corp.
> >> + */
> >> +
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/device.h>
> >> +#include <linux/init.h>
> >> +#include <linux/kernel.h>
> >> +
> >> +#include <dt-bindings/clock/r9a08g045-cpg.h>
> >> +
> >> +#include "rzg2l-cpg.h"
> >> +
> >> +/* RZ/G3S Specific registers. */
> >> +#define G3S_CPG_PL2_DDIV (0x204)
> >> +#define G3S_CPG_SDHI_DDIV (0x218)
> >> +#define G3S_CPG_PLL_DSEL (0x240)
> >> +#define G3S_CPG_SDHI_DSEL (0x244)
> >> +#define G3S_CLKSELSTATUS (0x284)
> >> +
> >> +/* RZ/G3S Specific division configuration. */
> >> +#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3)
> >> +#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
> >> +
> >> +/* RZ/G3S Clock status configuration. */
> >> +#define G3S_DIVPL1A_STS DDIV_PACK(CPG_CLKSTATUS, 0, 1)
> >> +#define G3S_DIVPL2B_STS DDIV_PACK(CPG_CLKSTATUS, 5, 1)
> >> +#define G3S_DIVPL3A_STS DDIV_PACK(CPG_CLKSTATUS, 8, 1)
> >> +#define G3S_DIVPL3B_STS DDIV_PACK(CPG_CLKSTATUS, 9, 1)
> >> +#define G3S_DIVPL3C_STS DDIV_PACK(CPG_CLKSTATUS, 10, 1)
> >> +#define G3S_DIV_SDHI0_STS DDIV_PACK(CPG_CLKSTATUS, 24, 1)
> >
> > The register at offset 0x280 is called CPG_CLKDIVSTATUS, so
> > you probably want to add and use a G3S-specific definition.
>
> I just used the already definition as there is no conflict at the moment,
> it points to the same offset and is almost identical in name. With this
> would you still prefer to have it separately ?
I think that would be clearer for the casual reader.
On RZ/G2L, there is a single CPG_CLKSTATUS register to monitor frequency
dividers and selectors.
On RZ/G3S, this register was split into separate registers to monitor
frequency dividers (CPG_CLKDIVSTATUS) and selectors (CPG_CLKSELSTATUS).
You had to add a new definition for the latter anyway.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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