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Message-ID: <867conerys.wl-maz@kernel.org>
Date: Mon, 18 Sep 2023 10:44:11 +0100
From: Marc Zyngier <maz@...nel.org>
To: Miguel Luis <miguel.luis@...cle.com>
Cc: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvmarm@...ts.linux.dev
Subject: Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
On Wed, 13 Sep 2023 19:52:08 +0100,
Miguel Luis <miguel.luis@...cle.com> wrote:
>
> Specify both _EL02 and _EL12 system registers.
>
> Signed-off-by: Miguel Luis <miguel.luis@...cle.com>
> ---
> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
> 1 file changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 9aa1c06abdb7..957afd97e488 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
> /* All _EL02, _EL12 registers */
> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
While I could see the problem with the EL2 registers, I'm not
convinced by this patch. Is there an actual case for non _EL02, non
_EL12 registers that are included in the two ranges above?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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