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Message-ID: <20230918-cassette-exclusion-b2ce53745a5c@wendy>
Date: Mon, 18 Sep 2023 13:53:13 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Yu Chien Peter Lin <peterlin@...estech.com>
CC: <paul.walmsley@...ive.com>, <palmer@...belt.com>,
<aou@...s.berkeley.edu>, <david@...hat.com>,
<akpm@...ux-foundation.org>, <alexghiti@...osinc.com>,
<bjorn@...osinc.com>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <ycliang@...estech.com>
Subject: Re: [PATCH v2 1/3] riscv: Improve PTDUMP to show RSW with non-zero
value
On Thu, Sep 14, 2023 at 09:40:25AM +0800, Yu Chien Peter Lin wrote:
> + val = st->current_prot & pte_bits[i].mask;
> + if (val) {
> + if (pte_bits[i].mask == _PAGE_SOFT)
> + sprintf(s, pte_bits[i].set, val >> 8);
> + else
> + sprintf(s, "%s", pte_bits[i].set);
> + } else
> + sprintf(s, "%s", pte_bits[i].clear);
> +
just a nit, but checkpatch in the automation is whinging that you have
forgotten to add {} around both branches if this if statement.
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