linux-kernel - [PATCH] arm64: dts: imx8mp: assign parent clock and rate for audio clocks

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Message-Id: <1695108775-22924-1-git-send-email-shengjiu.wang@nxp.com>
Date:   Tue, 19 Sep 2023 15:32:55 +0800
From:   Shengjiu Wang <shengjiu.wang@....com>
To:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
        kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        marex@...x.de, peng.fan@....com, alexander.stein@...tq-group.com,
        laurent.pinchart@...asonboard.com, aford173@...il.com,
        l.stach@...gutronix.de, Frank.Li@....com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, shengjiu.wang@...il.com
Subject: [PATCH] arm64: dts: imx8mp: assign parent clock and rate for audio clocks

Assign parent clock for audio AHB and AXI clocks, and assign
clock rate for audio PLL1 and PLL2.

Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6f2f50e1639c..8a8a2c4aff9f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -734,16 +734,26 @@ clk: clock-controller@...80000 {
 						  <&clk IMX8MP_CLK_A53_CORE>,
 						  <&clk IMX8MP_CLK_NOC>,
 						  <&clk IMX8MP_CLK_NOC_IO>,
-						  <&clk IMX8MP_CLK_GIC>;
+						  <&clk IMX8MP_CLK_GIC>,
+						  <&clk IMX8MP_CLK_AUDIO_AHB>,
+						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
+						  <&clk IMX8MP_AUDIO_PLL1>,
+						  <&clk IMX8MP_AUDIO_PLL2>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_ARM_PLL_OUT>,
 							 <&clk IMX8MP_SYS_PLL2_1000M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
-							 <&clk IMX8MP_SYS_PLL2_500M>;
+							 <&clk IMX8MP_SYS_PLL2_500M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>;
 				assigned-clock-rates = <0>, <0>,
 						       <1000000000>,
 						       <800000000>,
-						       <500000000>;
+						       <500000000>,
+						       <400000000>,
+						       <800000000>,
+						       <393216000>,
+						       <361267200>;
 			};
 
 			src: reset-controller@...90000 {
-- 
2.34.1