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Message-Id: <c5061fbe8ef9c4971cd45de7b5d8408dc1b848b4.1695189879.git.wangchen20@iscas.ac.cn>
Date: Wed, 20 Sep 2023 14:38:08 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
devicetree@...r.kernel.org, emil.renner.berthing@...onical.com,
guoren@...nel.org, jszhang@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, palmer@...belt.com,
paul.walmsley@...ive.com, robh+dt@...nel.org,
xiaoguang.xing@...hgo.com
Cc: Chen Wang <wangchen20@...as.ac.cn>
Subject: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.
Acked-by: Xiaoguang Xing <xiaoguang.xing@...hgo.com>
Signed-off-by: Chen Wang <wangchen20@...as.ac.cn>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
+ - thead,c920
- const: riscv
- items:
- enum:
--
2.25.1
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