linux-kernel - [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension

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Message-Id: <20230920074653.2509631-1-xiao.w.wang@intel.com>
Date:   Wed, 20 Sep 2023 15:46:51 +0800
From:   Xiao Wang <xiao.w.wang@...el.com>
To:     paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, ardb@...nel.org
Cc:     anup@...infault.org, haicheng.li@...el.com,
        ajones@...tanamicro.com, linux-riscv@...ts.infradead.org,
        linux-efi@...r.kernel.org, linux-kernel@...r.kernel.org,
        Xiao Wang <xiao.w.wang@...el.com>
Subject: [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension

Bitops optimization with specialized instructions is common practice in
popular ISAs, this patch set uses RISC-V Zbb extension to optimize four
bitops: __ffs, __fls, ffs and fls.

The first patch rearranges the content in hwcap.h cpufeature.h, it helps
to avoid a cyclic header including issue for patch 2.

The second patch leverages the alternative mechanism to dynamically apply
this optimization.

The series has following dependency:
https://lore.kernel.org/linux-riscv/20230918131518.56803-8-ajones@ventanamicro.com/

Thanks,
Xiao

v2:
- Remove the "EFI_" prefix from macro name "EFI_NO_ALTERNATIVE" to make it
  generic. (Ard)
- patch-1 is added, it's based on "RISC-V: Enable cbo.zero in usermode". (Andrew)

Xiao Wang (2):
  riscv: Rearrange hwcap.h and cpufeature.h
  riscv: Optimize bitops with Zbb extension

 arch/riscv/include/asm/bitops.h       | 266 +++++++++++++++++++++++++-
 arch/riscv/include/asm/cpufeature.h   |  83 ++++++++
 arch/riscv/include/asm/hwcap.h        |  91 ---------
 arch/riscv/include/asm/pgtable.h      |   1 +
 arch/riscv/include/asm/switch_to.h    |   2 +-
 arch/riscv/include/asm/vector.h       |   2 +-
 drivers/firmware/efi/libstub/Makefile |   2 +-
 7 files changed, 350 insertions(+), 97 deletions(-)

-- 
2.25.1