linux-kernel - Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

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Message-ID: <CAJF2gTTfpG=Hy9bhPjLVVvSt-t=Hgu2GFm_V8-VRLuaCmSpv0g@mail.gmail.com>
Date:   Wed, 20 Sep 2023 15:44:40 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Chen Wang <unicornxw@...il.com>
Cc:     aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
        devicetree@...r.kernel.org, emil.renner.berthing@...onical.com,
        jszhang@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        palmer@...belt.com, paul.walmsley@...ive.com, robh+dt@...nel.org,
        xiaoguang.xing@...hgo.com, Chen Wang <wangchen20@...as.ac.cn>
Subject: Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

On Wed, Sep 20, 2023 at 2:38 PM Chen Wang <unicornxw@...il.com> wrote:
>
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@...hgo.com>
> Signed-off-by: Chen Wang <wangchen20@...as.ac.cn>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
Reviewed-by: Guo Ren <guoren@...nel.org>

>            - const: riscv
>        - items:
>            - enum:
> --
> 2.25.1
>


-- 
Best Regards
 Guo Ren