linux-kernel - Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

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Message-ID: <20230920-borax-swipe-dbf4aa8ed4e2@wendy>
Date:   Wed, 20 Sep 2023 09:37:26 +0100
From:   Conor Dooley <conor.dooley@...rochip.com>
To:     Chen Wang <unicornxw@...il.com>
CC:     <aou@...s.berkeley.edu>, <chao.wei@...hgo.com>, <conor@...nel.org>,
        <devicetree@...r.kernel.org>, <emil.renner.berthing@...onical.com>,
        <guoren@...nel.org>, <jszhang@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <palmer@...belt.com>, <paul.walmsley@...ive.com>,
        <robh+dt@...nel.org>, <xiaoguang.xing@...hgo.com>,
        Chen Wang <wangchen20@...as.ac.cn>
Subject: Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

On Wed, Sep 20, 2023 at 02:38:08PM +0800, Chen Wang wrote:
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@...hgo.com>
> Signed-off-by: Chen Wang <wangchen20@...as.ac.cn>

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
>            - const: riscv
>        - items:
>            - enum:
> -- 
> 2.25.1
> 

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