linux-kernel - Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <IA1PR20MB495313B7E9B2FC529BE0BB2ABBF9A@IA1PR20MB4953.namprd20.prod.outlook.com>
Date:   Wed, 20 Sep 2023 19:24:21 +0800
From:   Inochi Amaoto <inochiama@...look.com>
To:     Conor Dooley <conor.dooley@...rochip.com>,
        Anup Patel <apatel@...tanamicro.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
        evicetree@...r.kernel.org, emil.renner.berthing@...onical.com,
        guoren@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, robh+dt@...nel.org,
        xiaoguang.xing@...hgo.com, Chen Wang <wangchen20@...as.ac.cn>,
        Inochi Amaoto <inochiama@...look.com>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint

>
>Yo,
>
>On Wed, Sep 20, 2023 at 05:08:41PM +0800, Inochi Amaoto wrote:
>>> On Wed, Sep 20, 2023 at 02:39:39PM +0800, Chen Wang wrote:
>>>> From: Inochi Amaoto <inochiama@...look.com>
>>>>
>>>> Add two new compatible string formatted like `C9xx-clint-xxx` to identify
>>>> the timer and ipi device separately, and do not allow c900-clint as the
>>>> fallback to avoid conflict.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
>>>> Signed-off-by: Chen Wang <wangchen20@...as.ac.cn>
>>>
>>> Have you ignored Krzysztof's comments on this? I don't see a response or
>>> a reaction to his comments about the compatibles on the last version.
>>> Additionally, where is the user for these? I don't see any drivers that
>>> actually make use of these.
>>>
>>
>> Sorry for late reply and wrong message-id.
>>
>> The clint is parsed by sbi.
>
>That needs to go in the commit message.

Yes, it will.

>
>> As use the same compatible, the opensbi will
>> parse the device twice. This will cause a fault.
>
>Then only have one compatible with 2 register ranges? Then your SBI
>implementation can use those two register ranges to find out the base
>address for the mtimer bits and for the mswi bits.
>I don't understand why this cannot be done, could you please explain.

That is a good idea, but now SBI use the second register ranges as
mtimecmp address for aclint. And there is a aclint-mswi in the SBI.
Maybe a change is needed?

>I also don't see anything in the opensbi repo right now that is using
>these (nor could I easily see any patches for opensbi adding this).
>Is there another SBI implementation that you are using that I can take
>a look at to try and understand this better?
>

This will be sumbit in a short time.
Now we only use it is sophgo vendor SBI, which url is [1].

[1] https://github.com/sophgo/opensbi

>>> Why do you need to have 2 compatibles (and therefore 2 devices) for the
>>> clint? I thought the clint was a single device, of which the mtimer and
>>> mswi bits were just "features"? Having split register ranges isn't a
>>> reason to have two compatibles, so I must be missing something here...
>
>> Sorry for late reply, The clint consists of mtimer and ipi devices, which
>> is defined in [1].
>
>Yes, I have looked at the spec. I went to check it again before replying
>here in case there was something immediately obvious that I was missing.
>

I think nothing missed.

>> This standard shows clint(or the aclint) has two device,
>
>The wording used here doesn't really matter. It's one interrupt
>controller that does mtimer and mswi.
>
>> but not one. In another word, there is no need to defined mtimer and ipi
>> device on the same base address.
>
>There's also no need to have two compatibles for the same interrupt
>controller, so I do not get this reasoning. What actually _requires_
>them to be split?
>

Yes, it is one, but can be mapped into different address. So I think we
need two.

>> So we need two compatibles to allow sbi to identify them correctly.
>
>Why is it not sufficient to identify the individual memory regions?
>

FYI, Anup. As I have no idea for aclint implementation.

>Thanks,
>Conor.
>