linux-kernel - [PATCH] ARM: dts: stm32: Fix ethernet pins used on phyCORE-STM32MP15

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20230920120520.2807275-1-s.hauer@pengutronix.de>
Date:   Wed, 20 Sep 2023 14:05:20 +0200
From:   Sascha Hauer <s.hauer@...gutronix.de>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        devicetree@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com,
        linux-kernel@...r.kernel.org, kernel@...gutronix.de,
        Sascha Hauer <s.hauer@...gutronix.de>, stable@...r.kernel.org
Subject: [PATCH] ARM: dts: stm32: Fix ethernet pins used on phyCORE-STM32MP15

On the phyCORE-STM32MP15 the 125MHz clock for the ethernet phy must
be provided on the ETH_RGMII_GTX_CLK. ETH_RGMII_CLK125 is unused though,
so remove the latter pin and add the former.

ethernet0_rgmii_pins_d and ethernet0_rgmii_sleep_pins_d are used by the
phyCORE-STM32MP15 board only, so we can do this change in the generic
pinctrl file without breaking other boards.

Fixes: 303f3fe1d88f ("ARM: dts: stm32: Add alternate pinmux for ethernet for stm32mp15")
Cc: stable@...r.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
---
 arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
index 098153ee99a3a..5d85bcc8b3a8c 100644
--- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
@@ -354,7 +354,7 @@ pins1 {
 
 	ethernet0_rgmii_pins_d: rgmii-3 {
 		pins1 {
-			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+			pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
 				 <STM32_PINMUX('G', 13, AF11)>,	/* ETH_RGMII_TXD0 */
 				 <STM32_PINMUX('G', 14, AF11)>,	/* ETH_RGMII_TXD1 */
 				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
@@ -384,8 +384,7 @@ pins3 {
 
 	ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
 		pins1 {
-			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
-				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+			pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
 				 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
 				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
 				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
-- 
2.39.2