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Date: Wed, 20 Sep 2023 15:09:52 +0200
From: Alvin Å ipraga <alvin@...s.dk>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
ipraga <alsi@...g-olufsen.dk>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 0/3] clk: si5351: add option to adjust PLL without glitches
From: Alvin Å ipraga <alsi@...g-olufsen.dk>
This series intends to address a problem I had when using the Si5351A as
a runtime adjustable audio bit clock. The basic issue is that the driver
in its current form unconditionally resets the PLL whenever adjusting
its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in
the clock output.
As a remedy, a new property is added to control the reset behaviour of
the PLLs more precisely. In the process I also converted the bindings to
YAML.
Alvin Å ipraga (3):
dt-bindings: clock: si5351: convert to yaml
dt-bindings: clock: si5351: add PLL reset mode property
clk: si5351: allow PLLs to be adjusted without reset
.../bindings/clock/silabs,si5351.txt | 126 --------
.../bindings/clock/silabs,si5351.yaml | 270 ++++++++++++++++++
drivers/clk/clk-si5351.c | 47 ++-
include/linux/platform_data/si5351.h | 2 +
4 files changed, 316 insertions(+), 129 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt
create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml
--
2.41.0
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