lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7f575fc3-f4d7-4c79-a13e-1b125093d8f3@intel.com>
Date:   Thu, 21 Sep 2023 15:56:12 -0700
From:   Dave Jiang <dave.jiang@...el.com>
To:     Jeongtae Park <jtp.park@...sung.com>,
        Dan Williams <dan.j.williams@...el.com>,
        Alison Schofield <alison.schofield@...el.com>,
        Vishal Verma <vishal.l.verma@...el.com>,
        Ben Widawsky <bwidawsk@...nel.org>,
        Jonathan Cameron <jonathan.cameron@...wei.com>,
        Davidlohr Bueso <dave@...olabs.net>,
        Fan Ni <fan.ni@...sung.com>, <linux-cxl@...r.kernel.org>
CC:     <linux-kernel@...r.kernel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Kyungsan Kim <ks0204.kim@...sung.com>,
        "Wonjae Lee" <wj28.lee@...sung.com>,
        Hojin Nam <hj96.nam@...sung.com>,
        Junhyeok Im <junhyeok.im@...sung.com>,
        Jehoon Park <jehoon.park@...sung.com>,
        "Jeongtae Park" <jeongtae.park@...il.com>
Subject: Re: [PATCH 4/7] cxl: Fix a checkpatch error



On 9/20/23 19:51, Jeongtae Park wrote:
> ERROR: Macros with complex values should be enclosed in parentheses
> 
> Signed-off-by: Jeongtae Park <jtp.park@...sung.com>

Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> ---
>  drivers/cxl/cxl.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 76d92561af29..545381355efb 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -142,7 +142,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
>  #define CXL_RAS_HEADER_LOG_OFFSET 0x18
>  #define CXL_RAS_CAPABILITY_LENGTH 0x58
>  #define CXL_HEADERLOG_SIZE SZ_512
> -#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
> +#define CXL_HEADERLOG_SIZE_U32 (SZ_512 / sizeof(u32))
>  
>  /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
>  #define CXLDEV_CAP_ARRAY_OFFSET 0x0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ