linux-kernel - Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint

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Date:   Thu, 21 Sep 2023 09:05:32 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Inochi Amaoto <inochiama@...look.com>
Cc:     Anup Patel <apatel@...tanamicro.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        aou@...s.berkeley.edu, chao.wei@...hgo.com,
        evicetree@...r.kernel.org, emil.renner.berthing@...onical.com,
        guoren@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, robh+dt@...nel.org,
        xiaoguang.xing@...hgo.com, Chen Wang <wangchen20@...as.ac.cn>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint

On Thu, Sep 21, 2023 at 08:43:47AM +0800, Inochi Amaoto wrote:

> >>>> but not one. In another word, there is no need to defined mtimer and ipi
> >>>> device on the same base address.
> >>>
> >>> There's also no need to have two compatibles for the same interrupt
> >>> controller, so I do not get this reasoning. What actually _requires_
> >>> them to be split?
> >>>
> >>
> >> Yes, it is one, but can be mapped into different address. So I think we
> >> need two.
> >
> >Not two compatibles though, just two memory addresses that you need to
> >locate (or maybe even 3, for SSWI?)
> >
> 
> We may need four (mtime, mtimecmp, mswi, sswi) if use register range.

Why would you need 4? The first two certainly could be individual
reg entries, no?

> Anyway, I will use a vendor spec implementation as a temporary solution.
> I hope this will be corrected in a predictable future, and we can use a
> standard way to resolve this at that time. :)

If the spec doesn't get frozen, there'll not be a standard way merged.
Hopefully not too many others go off an implement non-frozen specs, and
we will not really need to worry all that much about it.

Cheers,
Conor.

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